Approximate computing provides an emerging approach to design high performance and low power arithmetic circuits. The logarithmic multiplier (LM) converts multiplication into addition and has inherent approximate characteristics. In this article, dynamic range approximate LMs (DR-ALMs) for machine learning applications are proposed; they use Mitchell’s approximation and a dynamic range operand truncation scheme. The worst case (absolute and relative) errors for the proposed DR-ALMs are analyzed. The accuracy and the hardware overhead of these designs are provided to select the best approximate scheme according to different metrics. The proposed DR-ALMs are compared with the conventional LM with exact operands and previous approximate multipliers; the results show that the power-delay product (PDP) of the best proposed DR-ALM (DR-ALM-6) are decreased by up to 54.07 percent with the mean relative error distance (MRED) decreasing by 21.30 percent compared with 16-bit conventional design. Case studies for three machine learning applications show the viability of the proposed DR-ALMs. Compared with the exact multiplier and its conventional counterpart, the back-propagation classifier with DR-ALMs with a truncation length larger than 4 has a similar classification result for the three datasets; the K-means clustering application with all DR-ALMs has a similar clustering result for four datasets; and the handwritten digit recognition application with DR-ALM-5 or DR-ALM-6 for LeNet-5 achieves similar or even slightly higher recognition rate.

Radix-4 Booth encoding provides ease in the generation of partial products, thus is widely used to achieve power-efficient and low-area signed multipliers. Conversely, the radix-8 Booth encoding exhibits low-performance as it requires generation of odd multiples of the multiplicand. In this brief, this issue is addressed by approximating the odd multiples of radix-8 to their nearest power of two such that the errors complement each other. In the pursuit of an accuracy-energy trade-off, hybrid low radix (HLR) based two approximate Booth multipliers (HLR-BM1 and HLR-BM2) are designed. HLR-BM2, compared to the previous best error-optimized design (ABM1), achieved a reduced energy of 22% with a comparable MRED. Moreover, HLR-BM2 achieves an improvement of 75% in MRED and 11% in energy consumption compared to the previously best energy-optimized design (RAD64). As a case study, performance for image transformation is evaluated. A high peak signal-to-noise ratio (PSNR, close to 50dB) is obtained for the proposed multiplier designs.

In this brief, hybrid partial product-based building blocks are proposed by considering the probability distribution of the input operands. An efficient hardware implementation of approximate 4x4 multipliers is achieved while maintaining a required accuracy. Moreover, high-performance approximate NOR-based half adder (NxHA) and full adder (NxFA) cells are proposed for use in a 4x4 multiplier. Three different strategies (Ax8-1/2/3) are further proposed and analyzed for utilizing the 4x4 multipliers when designing larger multipliers. Ax8-2 provides the best trade-off among the designs with a moderate MRED. A reduction of 30% and 17% in the MRED is achieved compared to previous best energy-optimized and MRED-optimized designs. Among the designs with higher MREDs, Ax8-3 exhibits the smallest MRED and PDP. Moreover, it shows an improvement of 7% to 28% in delay compared to existing approximate recursive designs. As a case study, image multiplication is evaluated; a high peak signal-to-noise ratio (PSNR) with a value close to 50dB is obtained for the proposed multiplier designs.

The focus of existing designs on approximate radix-8 Booth multipliers has been on ASIC-based platforms. These multipliers are based on an approximation as defined for ASIC-based systems, so they cannot achieve comparable performance gains when used for FPGA-based hardware accelerators. This is due to the inherited architectural differences between FPGAs and ASICs. This brief bridges this gap by proposing high-performance approximate radix-8 Booth multipliers whose designs target FPGA-based systems. Hence, two approximate radix-8 Booth multipliers (referred to as AxBM1 and AxBM2) are proposed. Approximation is implemented such that the 6-input lookup table (LUT) and the associated carry chains of the FPGAs are fully utilized. AxBM2 exhibits 49% improvement in delay compared to the previous best FPGA-targeted design (Booth-Approx). AxBM2 has the advantage of complementing errors; this feature has been combined with truncation to achieve up to 60% in energy savings. Moreover, the resolution of the previous state-of-the-art error-energy Pareto front is improved, such that better energy gains can be achieved for a given error constraint. As a case study, the proposed multipliers are applied to the application of Sobel edge detection, AxBM2 detected 98.45% edges with energy savings of 26.41%.

Approximate computing has emerged as a new paradigm that provides power-efficient and high-performance arithmetic designs by relaxing the stringent requirement of accuracy. Nonlinear functions (such as softmax, rectified linear unit (ReLU), Tanh, and Sigmoid) are extensively used in deep neural networks (DNNs). However, they incur significant power dissipation due to the high circuit complexity. As DNNs are error-tolerant, the design of approximation-linear functions is possible and desired. In this article, the design of an approximate softmax function (AxSF) is proposed. AxSF is based on a double hybrid structure (DHS). AxSF divides the input of the softmax function into two parts for different processing methods. The most significant bits (MSBs) are processed with lookup tables (LUTs) and an exact restoring array divider (EXDr). Taylor’s expansion and a logarithmic divider are used for the less significant bits (LSBs). An improved DHS (IDHS) is also proposed to reduce the hardware complexity. In IDHS, a novel Booth multiplier is utilized for the hybrid scheme to improve the partial product generation and compression, while the truncated implementation is applied to the divider unit. The proposed DHS and IDHS are compared with existing softmax designs. The results show that the proposed approximate softmax design reduces hardware by 48% and delay by 54% while retaining a high accuracy.

Recursive multipliers (RMs) have been classified as a class of low-power multipliers because they provide a wide-range of power-quality configuration options. 2×2 multipliers are the constitutional building blocks of this recursive topology; however, most of the state-of-the-art approximate recursive designs are based on a 4×4 building blocks. Therefore, the design space exploration of AxRMs using 2×2 multipliers is still an open-research problem. To add the configurability and flexibility in the design of AxRMs such 2-bit multipliers are required that exhibit high-performance and low-area. In this article, two approximate 2×2 multipliers are proposed that exhibit double-sided error distribution feature. Compared to the existing best-approximated 2×2 multiplier, the proposed design achieves a reduction of 52 percent in area and exhibits an improvement of 25 percent in terms of delay while having a bounded error behavior. Then, three 8×8 multipliers of variable accuracy are designed using different configurations of approximate 2×2 multiplier. AxRM1 is the most-accurate design; an improvement of 50 percent in terms of mean relative error distance (MRED) is achieved compared to the existing best MRED-optimized design. AxRM3 has similar MRED compared to the previous best 2×2-based AxRM (called MACISH); however, AxRM3 exhibits 13 percent better PDP than MACISH due to the use of low-power and high-performance 2×2 multipliers in building larger multipliers. The proposed approximate multipliers are applied to cutting-edge error-tolerant application, i.e., convolutional neural networks. AxRM2 provides the best quality-power trade-off, 32.64 percent power savings are achieved with 1.10 percent better classification accuracy.