This article proposes a complete three-input gate library using atomic silicon quantum dots made of silicon dangling bonds.

Coarse Grain Reconfigurable Architectures (CGRAs) are an emerging hybrid computational architecture that has the parallel customization benefits of low-level logic devices such as FPGAs and ASICs, while the relative coarseness of these architectures makes CGRAs easier to design for, which is more similar to the traditional processor. In the process of mapping designs to CGRAs, flexible, fast, and adaptive Placement and Routing (P&R) is fundamental in order to implement efficient run-time reconfigurable frameworks. It is well-known that P&R is an NP-complete problem, and thus, solutions rely on heuristics to achieve quality results with acceptable execution times. CGRA P&R has different constraints compared to traditional VLSI P&R, e.g. path latency balancing and modulo scheduling of loops. In this work, we propose a graph-based P&R approach that uses graph traversals to map designs to CGRAs. Additionally, we parallelize our approach with a graph-based greedy heuristic that executes on a GPU. We compare our proposed P&R approach with the CGRA-ME framework, which implements Simulated Annealing and Integer Linear Programming placement algorithms. Our results show that this new approach can generate optimal mappings and improve the execution run-time up to several orders of magnitude. Furthermore, considering spatial mapping at the millisecond scale, our GPU approach is one order of magnitude faster compared to the state-of-the-art tool VPR.

The advent of the Internet of Things (IoT) has revolutionized the way we, as a society, perform different daily tasks, such as healthcare. The Internet of Health Things (IoHT) is an example of the IoT specialization handling sensitive user data and applications requiring solutions to address different security and privacy issues. IoHT requires security mechanisms in communication. However, these mechanisms need to consider the limitations of the IoHT devices and communication. Hence, symmetric cryptography is suitable to IoHT once it uses less computational and communication resources than asymmetric cryptography. But, symmetric cryptography relies on the agreement of the cryptography material (e.g., the cryptography key) among the devices, a challenge in networks with resource constraints, such as IoHT. Therefore, this article presents a Low memORy symmEtric-key geNerAtion (LORENA) method based on group secret key agreement protocol for IoHT environments. Evaluations have focused on computational efficiency, data security requirements, and scalability in a network with up to ten devices per group using a simulator and a device with limited computational resources. Results show that the protocol is lightweight, secure, and feasible to IoHT networks, presenting a linear growth in the 128-bit key distribution time for each device entering the group.