With the current technological transformation in the automotive industry, autonomous vehicles are getting closer to the Society of Automative Engineers (SAE) automation level 5. This level corresponds to the full vehicle automation, where the driving system autonomously monitors and navigates the environment. With SAE-level 5, the concept of a Shared Autonomous Vehicle (SAV) will soon become a reality and mainstream. The main purpose of an SAV is to allow unrelated passengers to share an autonomous vehicle without a driver/moderator inside the shared space. However, to ensure their safety and well-being until they reach their final destination, active monitoring of all passengers is required. In this context, this article presents a microphone-based sensor system that is able to localize sound events inside an SAV. The solution is composed of a Micro-Electro-Mechanical System (MEMS) microphone array with a circular geometry connected to an embedded processing platform that resorts to Field-Programmable Gate Array (FPGA) technology to successfully process in the hardware the sound localization algorithms.

Computer systems are permanently present in our daily basis in a wide range of applications. In systems with mixed-criticality requirements, e.g., autonomous driving or aerospace applications, devices are expected to continue operating properly even in the event of a failure. An approach to improve the robustness of the device's operation lies in enabling fault-tolerant mechanisms during the system's design. This article proposes Lock-V, a heterogeneous architecture that explores a Dual-Core Lockstep (DCLS) fault-tolerance technique in two different processing units: a hard-core Arm Cortex-A9 and a soft-core RISC-V-based processor. It resorts a System-on-Chip (SoC) solution with software programmability (available trough the hard-core Arm Cortex-A9) and field-programmable gate array (FPGA) technology, taking advantages from the latter to support the deployment of the RISC-V soft-core along with dedicated hardware accelerators towards the realization of the DCLS.

The Internet of Things (IoT) is enabling the connection of an infinity of physical objects to the Internet through the wide deployment of low-end embedded devices at the network edge. However, providing communication capabilities to such devices, which allows them to connect to the Internet seamlessly, is not straightforward. Such features require the adoption of a lightweight and standard network stack, commonly integrated with an embedded operating system (OS), mitigating the complexity of developing resource-constrained wireless nodes. To assist in such tasks, some existing motes explore reconfigurable technology to accelerate compute-intense tasks (application- or network-related) in dedicated hardware accelerators. This article describes the deployment of a real-time OS, RIOT, on a reconfigurable end-device architecture for IoT, the CUTE Mote. The CUTE mote is based on a heterogeneous solution that combines a hard-core microcontroller unit beside reconfigurable technology and an IEEE 802.15.4-compliant radio transceiver.