Rajkumar Sarma

Dr. Rajkumar Sarma

Electrical and Electronic Engineering, University of Galway, Galway, Ireland
orcid

Research Focus & Metrics

Academic Career Length

15Years (2012-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 August 2014
Verified
Conference Paper
Closed access
HEHelga Evangelene
Helga Evangelene
Rajkumar SarmaRajkumar Sarma
Rajkumar Sarma
This paper presents a low power hybrid flip flop using sleepy stack inverter pair for retaining the logic level till the end of evaluation and pre-charge phase of the flip flop. The sleepy stack inverter pairs are efficient in leakage power reduction and overall power dissipation as the technology scales down to 90nm and below. The performance of the proposed flip flop was compared with the conventional dual dynamic node pulsed hybrid flip flop (DDFF) which uses conventional static CMOS inverter pairs in cadence virtuoso 90nm tool. It shows 20% reduction in total power consumed with 89% reduction in leakage power at its output node. T flip flop, SR flip flop and JK flip flop were designed using this proposed D flip flop and its performance was compared with flip flops designed using DDFF. As the proposed flip flops have improved performance in terms of leakage power, total power and power delay product at high speed, it can be widely used in high performance applications.

1 April 2018
Verified
Conference Paper
Closed access
MSManendra Singh
Manendra Singh
Rajkumar SarmaRajkumar Sarma
Rajkumar Sarma
A high performance MOSFET current mirror in a folded cascade configuration is design to achieve a high output resistance. The design has both n and p type MOSFET for current feedback between gate and source in order to achieve a constant drain current. In the discussed circuits we have found out the range of currents for which the circuit is showing amplification and mirroring effect. We need high output impedance so to drive more circuitry from it and the current mirror is the circuit that implements the principle that if a gate-source voltage of two uniforms MOS transistors is same then their channel current flowing would be equal. We have implemented the folded cascode current mirror where the range of current on which the circuit is mirroring the current ranges from 100mV to 700mV. The circuit is implemented on cadence virtuoso 180nm technology with 1.8V supply voltage.

1 April 2014
Verified
Conference Paper
Closed access
SPShivendra Pandey
Shivendra Pandey
AKAfshan Amin Khan
Afshan Amin Khan
Rajkumar SarmaRajkumar Sarma
Rajkumar Sarma
This paper present a comparison between the design of the 8T adder based Carry Select Adder (CSA) and 10T adder based CSA. Using both the designs of adders 4-bit CSA architecture has been developed and compared with the 28T adder 4-bit CSA. The 10T CSA design has reduced delay, power and area as compared with the 28T CSA with a slight tradeoff for area as compared to 8T CSA. The analysis shows that the 10T CSA is better than both 8T adder based CSA and 28T CSA. This work evaluates the performance of the 10T CSA design in terms of power, delay and area using 180nm CMOS process technology Cadence Virtuoso tool and Spectre simulator.

29 November 2016 in Far East Journal of Electronics and Communications
Verified
Journal Article
Closed access
ADAmarveer Kaur Dhindsa
Amarveer Kaur Dhindsa
Rajkumar SarmaRajkumar Sarma
Rajkumar Sarma

1 May 2015
Verified
Conference Paper
Closed access
NBN. Jithendra Babu
N. Jithendra Babu
Rajkumar SarmaRajkumar Sarma
Rajkumar Sarma
At the present days, the low power designs are playing a vital role in every designs. Due to the existence of the battery designs in the integrated circuits the low power designs play a major role of operations in any circuit. In this paper our work is on a low power and high speed Multiply-accumulate unit that is the basic block in digital processing systems. Since, the basic blocks of MAC unit are multiplier, adder and accumulator. The design of these blocks should be efficient in terms of the power and speed. So our work is based on the BCD multiplication and addition and also to find the floating point numbers. Our implementation consists of multiplier, register, binary to BCD converter; Adder and BCD block which make the overall output of the MAC to be in the BCD format. First the individual blocks are designed and analyzed and the overall MAC is implemented in Cadence 0.9μm technology and power and delay analysis is done using the cadence spectre.