Quantum-dot cellular automata (QCA) nanotechnology is a practical suggestion for replacing present silicon-based technologies. It provides many benefits, such as low power usage, high velocity, and an extreme density of logic functions on a chip. In contrast, designing circuits with no waste of information (reversible circuits) may further reduce energy losses. The Feynman gate has been recognized as one of the most famous QCA-based gates for this purpose. Since reversible gates are significant, this paper develops a new optimized reversible double Feynman gate that uses efficient arithmetic elements as its key structural blocks. Additionally, we used several modeling principles to make it consistent and more robust against noise. Moreover, we examined the suggested model and compared it to the previous models regarding the complexity, clocking, number of cells, and latency. Furthermore, we applied QCADesigner to monitor the outline and performance of the proposed gate. The results show an acceptable improvement via the designed double Feynman gate in comparison to the existing designs. Finally, the temperature and cost analysis indicated the efficiency of the proposed nan-scale gate.

The very-large-scale-integration industry has been highly trying to attain miniaturization. This function causes several challenges regarding size, switching speed, power, and fault-tolerant at the nanoscale. Quantum-dot cellular automata (QCA) can contain a remarkable reduction in scale, fast switching rate, ultra-low energy consumption, and high fault-tolerant. Thus, fault-tolerant logic has attained the attention of several investigators in the QCA science domain. On the other hand, a binary-to-gray converter converts the input data to the gray number to facilitate error correction in digital communication. So, in the present investigation, we have demonstrated a structure of fault-tolerant binary-to-gray converter in QCA employing the majority gate, inverter gate, and cell redundancy on the wire. With the utilization of the QCADesigner 2.0.3 simulator, we have simulated and tested proposed circuits. In this paper, four factors, namely single-cell missing, displacement, misalignment, and extra single-cell, have been inspected by simulation software. The proposed fault-tolerant two-bit, three-bit, and four-bit binary-to-gray converter could attain 100% fault tolerance while a single missing defect existed in the layout.