We propose a novel co-packaged optical transceiver architecture capable of operating at 112 Gbaud per lane and scalable to 1.6 Tb/s capacity and beyond for next generation 51.2T and 102.4T digital switches.

In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (<15 μm).

Managing insertion losses, polarizations and device footprint is crucial in developing large-scale photonic integrated circuits (PICs). This paper presents a solution to these critical challenges by designing a semiconductor optical amplifier (SOA) in the O-band with reduced polarization sensitivity, leveraging the ultra-compact InP Membrane on Silicon (IMOS) platform. The platform is compatible with close integration atop electronics, via densely populated vertical interconnects. The SOA incorporates a thin tensile-strained bulk active layer to mitigate polarization sensitivity. The developed 500 μm long SOA has a peak gain of 11.5 dB at 1350 nm and an optimal polarization dependency of less than 1 dB across a 25 nm bandwidth, ranging from 1312 nm to 1337 nm. The device is practical for integrated circuits where multiple amplifiers work in cascades with a minimal 6.5 dB noise figure (NF) measured at the gain peak. The designed vertical active-passive transition, achieved through inverse tapering, allows for effective field coupling in the vertical direction resulting in a transmission efficiency of over 95% at the transition and minimal polarization sensitivity of less than 3%. The device yields significant gain at a small current density of less than 3 kA/cm² as the result of minimalist gain medium structure, reducing joule heating and improving energy efficiency. This is especially relevant in applications such as optical switching, where multiple SOAs populate the PIC within a small area. Consequently, the simulated and fabricated low polarization sensitive O-band SOA is a suitable candidate for integration into large-scale, ultra-compact photonic integrated circuits.

Optical switches (OS) are vital for meeting modern data centers’ capacity and latency needs, overcoming the bandwidth and speed limitations that electronic switches encounter. To this end, this work proposes a semiconductor optical amplifier (SOA)-based OS on the IMOS, a unique platform with a combination of high refractive index contrast for compactness and monolithic active-passive integration for active functionalities, thereby enabling the creation of compact SOA-based OSes. An 8 × 8 Banyan SOA-based OS is integrated on a 4 × 4 mm² area on the standard 4 × 6 mm² IMOS cell. This marks the first application of the IMOS technology platform for SOA-based OSes and sets the stage for compact and large-scale monolithic photonic integrated OS circuits. The basic 2 × 2 switch module delivers a high optical signal-to-noise ratio (OSNR) and an extinction ratio (ER) above 45 dB. Employing NRZ-OOK routing on the 2 × 2 basic OS module, a 15 dB input power dynamic range (IPDR) is achieved within a 1 dB power penalty at 12.5 Gb/s. Data routing at higher data rates of 25 Gb/s and 40 Gb/s incurs power penalties of 0.8 and 1.4 dB, respectively. Furthermore, data routing for a 3-stage 8 × 8 switch operating at 25 Gb/s results in a power penalty of 1.2 dB. Compared to the 1-stage 2 × 2 switch, only a 0.4 dB additional penalty is observed despite incorporating 2 additional SOAs in the cascade. This indicates that the switch can scale to higher radix to accommodate multi-stage switches with numerous ports, large bandwidth, and fast speed, which is essential in modern large-scale data centers.

The fast-maturing photonic integration technology is calling for a versatile platform that supports both active and passive functions as well as high scalability through component miniaturization. Indium phosphide (InP) has long been recognized for its ability to deliver a comprehensive suite of photonic components. InP membrane technology has emerged as a next-generation solution that could unite the functional completeness with high scalability. This paper describes recent advancements in the InP-membrane-on-Si (IMOS) platform, which supports high-performance passives, polarization and mode handling, native light sources, amplifiers, modulators and detectors, and novel material integration.

Indium–phosphide membrane on silicon is a nanophotonics platform which allows for monolithic integration of sub-micron nanophotonic waveguide circuits with native and efficient amplifiers and lasers. Active devices such as amplifiers have a high topography that requires a thick dielectric layer for planarization and wafer bonding, which poses challenges in thermal dissipation. Herein, we comprehensively analyzed the performance of distributed feedback lasers (DFBs) bonded on Si using a 2 µm-thick benzocyclobutene (BCB) layer, and with and without a 5 µm-thick gold thermal shunt to the substrate for efficient thermal dissipation. The thermal resistance of shunted devices is 176 and 115 K W⁻¹ for 0.5 mm and 0.75 mm lengths, respectively, which is a 2× improvement compared to reference membrane devices with no thermal shunt. This thermal resistance is maintained across various BCB thicknesses up to 30 µm, ensuring the possibility of using such devices for scalable 3D integration on other platforms or with electronics. Moreover, we showed that the thermal resistance value is around 110–120 K W⁻¹ for 0.75 mm-long shunted DFBs having array density values in the range of 40–200 µm, and that the temperature rise at the end of the DFB contact is as low as 1.3 °C at 8 kA cm⁻² driving current. Both of these characteristics demonstrate the density scaling potential of these nanophotonic devices.