Sergey Mosin

Prof. Sergey Mosin

Kazan Federal University, Kazan’, Russia
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Academic Career Length

24Years (2003-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 June 2017
Verified
Conference Paper
Closed access
VBVadim Belov
Vadim Belov
SMSergey Mosin
Sergey Mosin
Implementation of an efficient turbo decoder with low complexity, short delay and insignificant performance degradation is currently a quite challenging task. The paper presents an implementation of a 3GPP TS 36.212 LTE turbo decoder. The design of the turbo decoder has been optimized to achieve efficient FPGA resource utilization. This design can be useful for applications, which is critical to resource utilizations, but do not need high throughput.
1 March 2020
Verified
Conference Paper
Closed access
ZKZufar Kayumov
Zufar Kayumov
DTDmitrii Tumakov
Dmitrii Tumakov
SMSergey Mosin
Sergey Mosin
The use of a combination of a convolutional neural network and multilayer perceptrons for recognizing handwritten digits is considered. Recognition is carried out by two sets of networks following each other. The first neural network selects two digits with maximum activation functions. Depending on the winners, the following network is activated (multilayer perceptron), which selects one digit from two. The proposed algorithm is tested on the data from MNIST. The recognition error is 0.75%. Obtained results demonstrate that the minimum error with this approach is 0.68%, and the accuracy of the F-metric is about 0.99 for each digit. The main feature of the proposed solution is dealt with the fact that the proposed cascaded combination of neural networks provides a sufficiently high accuracy with a simple architecture.
1 September 2013
Verified
Conference Paper
Closed access
SMSergey Mosin
Sergey Mosin
The methodology to computer-aided design-for-testability (DFT) of mixed-signal IC is proposed. Functional model of DFT-automation is presented as IDEF0-diagram based on the system analysis. The purpose and principal realization of the key DFT processes in the model are considered. The decision criterions of effective DFT-solution for particular mixed-signal circuit design are proposed. The features of testing circuitries library are descried. Experimental results of the methodology application for analog-digital ADPCM codec are presented.
1 September 2018
Verified
Conference Paper
Closed access
SMSergey Mosin
Sergey Mosin
Wireless sensor networks (WSN) organized according to the IoT paradigm become more and more claimed in different sectors of economy. Power consumption and time of autonomous operating for wireless sensors are the key factors at designing reliable and sustainable systems. Mathematical models describing different physical and behavior aspects of the WSN play important role at the design automation. The important characteristics for several low-power communication standards and technologies are considered and compared. The features of wireless communication standards such as BLE, ZigBee, SIGFOX and LoRaWAN used for WSN implementation are demonstrated. The model describing the LoRaWAncommunication between end-devices and the network server in the Class A which can be used for the design automation purpose to select the effective architecture of the WSN and lifetime evaluation for the sensors is proposed.
1 September 2017
Verified
Conference Paper
Closed access
SMSergey Mosin
Sergey Mosin
Fault simulation is very important task for testing and fault diagnostics based on the concept of simulation before test. Catastrophic and parametric faults as well as component tolerances can make strong or weak influence on a correct circuit behavior. Therefore it is necessary to estimate such influence during design stage in order to provide high quality testing and diagnosis for the circuit under test. The number of potential faults in analog circuits is tremendous and the fault simulation requires essential computational resources as well as takes much time. The approach to the fault simulation in analog circuits based on parallel paradigm providing automation of the design-for-testability concept and essential reduction of the fault simulation time is proposed. The decomposition of the fault simulation task according to parallel paradigm is presented. The architecture of parallel simulation system is considered, and FSM for operation of the main host and executive nodes are described. Two scenarios of possible interoperability between the main host and executive nodes based on cascade scheme and deferred scheme are proposed. Experimental results for both scenarios are presented.
5 January 2006
Verified
Conference Paper
Closed access
SMSergey Mosin
Sergey Mosin