In recent years, multilevel inverters (MLIs) have emerged to be the most empowered power transformation technology for numerous operations such as renewable energy resources (RERs), flexible AC transmission systems (FACTS), electric motor drives, etc. MLI has gained popularity in medium- to high-power operations because of numerous merits such as minimum harmonic contents, less dissipation of power from power electronic switches, and less electromagnetic interference (EMI) at the receiving end. The MLI possesses many essential advantages in comparison to a conventional two-level inverter, such as voltage profile enhancement, increased efficiency of the overall system, the capability of high-quality output generation with the reduced switching frequency, decreased total harmonic distortions (THD) without reducing the power of the inverter and use of very low ratings of the device. Although classical MLIs find their use in various vital key areas, newer MLI configurations have an expanding concern to the limited count of power electronic devices, gate drivers, and isolated DC sources. In this review article, an attempt has been made to focus on various aspects of MLIs such as different configurations, modulation techniques, the concept of new reduced switch count MLI topologies, applications regarding interface with renewable energy, motor drives, and FACTS controller. Further, deep insights for future prospective towards hassle-free addition of MLI technology towards more enhanced application for various fields of the power system have also been discussed. This article is believed to be extremely helpful for academics, researchers, and industrialists working in the direction of MLI technology.

This work presents a novel control technique for proportional power sharing among parallel VSCs connected to an islanded Microgrid in a distributed generation system consisting of Photovoltaic (PV) and Solid Oxide Fuel Cell (SOFC) as two micro-sources. For tracking the maximum solar energy, a Seeker Optimized Fuzzy based Dynamic PI (FSOA-DPI) controller is implemented for the Modified Perturb and Observe MPPT method. Again, for the optimum cost management of the Microgrid system, DPI controller based decentralized Virtual Impedance Drooping (VID) technique is implemented for suitable load sharing between the two hybrid micro-sources. An Energy Storage System (ESS) regulated by FSOA-DPI controller is also proposed for this Microgrid system to ensure the better transient and sub-transient stability during fault occurrence. The dynamic response and stability of the system with proposed method is compared and contrasted with conventional PI controller based method during load sharing for ensuring the robust control under conditions of nonlinear load and faults. The harmonic analysis has been carried out by Fast Fourier Transform (FFT) and the values indicate that the Total Harmonic Distortion (THD) is well within the prescribed IEEE standard limits. Validation and justification of the improvements achieved by the proposed controller are realized using Matlab/Simulink environment.

Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the viable solutions toward scaling down below sub-7nm technology nodes. In this work, we compare electrical performance, including variability studies of several horizontal nanosheet transistors toward transistor structure optimization. We explore the impacts of nanosheet width and thickness on the electrical performance and outline important design guidelines necessary for vertically stacked nanosheet FETs. An increase in the complexity of the stacked nanosheet structures can lead to significant device variability. Using numerical simulation, we study the characteristics fluctuations induced by the random discrete dopants (RDD) and metal grain granularity (MGG) in nanosheet gate-all-around (GAA) transistors. We use 3-D quantum-mechanically corrected transport models in the simulation. It is observed that the σV_TH due to MGG variability is 12% higher than RDD variability while the RDD variability strongly influences the I_ON. The statistical simulation results predict that the presence of combined variability due to RDD and MGG strongly influences the threshold voltage variation (σV_TH) in nanoscale devices. This approach may be applied to the different types of variability, the geometry of the device, including the vertical and lateral dimensions of the transistor, and biasing conditions.

Using physics-based predictive technology CAD simulations, we show the improvements possible in device performance via strain engineering in vertically-stacked horizontal gate-all-around nanosheet Field-Effect transistors (NSFETs), which may outperform conventional FinFETs beyond 7 nm technology node. Effects of mechanical strain on NSFET variability is reported for the first time. We present a novel simulation approach for the analyses of random dopant fluctuation (RDF) and metal grain granularity (MGG) dependent variability in nanosheet transistors. The study encompasses topography simulation, which realistically reproduces a reported experimental nanosheet transistor. Device simulations are based on sub-band Boltzmann transport with 2D Schrödinger equation in the nanosheet cross-section and 1D Boltzmann transport along the nanosheet channel. The effects of mechanical stress and geometry dependence of the electrical characteristics are also reported. Critical design issues are outlined.

Feasibility of vertically-stacked silicon nanosheet FETs (SNS-FETs) for extreme scaling at 3nm technology node are investigated for the first time as one of the possible solutions to continue to enhance the performances of the CMOS technology. With the end of happy scaling era, change of device architecture has raised integration complexity along with several sort channel effects, mobility degradation, variability and quantum tunneling leakage. These are the major challenges as device dimensions are scaled for ultimate scaling below 7nm technology nodes. Towards low power and high speed (More-than-Moore applications), nanowires and nanosheet transistors are being proposed. Today, the question of FinFET downscaling is still open and more than ever alternatives to CMOS transistors, such as, vertically-stacked SNS-FETs are showing their potential to surpass the FinFETs. In this work, we use 3-D predictive simulations to study the performance potential of SNS-FETs at 3nm technology node.