Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5× in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure $>\mathsf{10}\times$>10× higher throughput and $>\mathsf{100}\times$>100× lower latency under comparable accuracy and power envelopes.

Efficiently computing Deep Neural Networks (DNNs) has become a primary challenge in today's computers, especially on devices targeting mobile or edge applications. Recent progress on Post-Training Quantization (PTQ) and Quantization-Aware Training (QAT) has shown that the key to high energy efficiency lies in executing deep learning models with low- (8- to 5-bit) or ultra-low-precision (4- to 2-bit). Unfortunately, current Central Processing Unit (CPU) architectures and Instruction Set Architectures (ISAs) present severe limitations on the range of data sizes supported to compute DNN kernels. In this work, we present Mix-GEMM, a hardware-software co-designed architecture that enables RISC-V processors to efficiently compute arbitrary mixed-precision DNN kernels, supporting all data size combinations from 8- to 2-bit. By applying binary segmentation, our architecture can scale its throughput by decreasing the data size of the operands, resulting in a flexible approach capable of leveraging state-of-the-art QAT and PTQ to achieve high energy efficiency at a very low cost. Evaluating our Mix-GEMM architecture in a dual-issue in-order RISC-V processor shows that we are able to boost its performance and energy efficiency by up to $44\times$ and $11\times$ with respect to the baseline processor, with an area overhead of only 2%. This allows our extended processor to execute state-of-the-art DNNs with significantly higher performance and energy efficiency than the standard FP32 precision, while retaining almost the same model accuracy.

In this work, we present a modular software subsystem that exposes a set of APIs for supporting the automation of a set of design choices in the synthesis of a hardware accelerator by a proprietary FPGA toolchain. We model the subsystem around Vivado, Xilinx's proprietary FPGA toolchain, in order to provide a finer grained control on the toolchain's features with respect to the standard .tcl interface. In order to do so, we focus on parsing the synthesis process' output as it happens, on automatically managing the toolchain's execution lifecycle, and on generating appropriate input .tcl scripts to interact with the standard APIs. On top of this subsystem, we extend polyFPGA, a framework for the FPGA acceleration of Iterative Stencil Loops (ISLs) that relies on Vivado. polyFPGA adopts the polyhedral model as a way to map a piece of input code to a queue of computational units, the Streaming Stencil Time-steps (SSTs), deployed on the target system. We show how the presented software subsystem allows the automation of the design space exploration (DSE) of a set of the synthesized architecture's hyperparameters, such as the queue's length and architecture's frequency, in a feedback based fashion, thanks on the information coming from the synthesis process and a set of user defined policies.