Recent advances in large language models have demonstrated their potential for automated generation of hardware description language (HDL) code from high-level prompts. Researchers have utilized fine-tuning to enhance the ability of these large language models (LLMs) in the field of Chip Design. However, the lack of Verilog data hinders further improvement in the quality of Verilog generation by LLMs. Additionally, the absence of a Verilog and electronic design automation (EDA) script data augmentation framework significantly increases the time required to prepare the training dataset for LLM trainers. This paper proposes an automated design-data augmentation framework, which generates high-volume and high-quality natural language aligned with Verilog and EDA scripts. For Verilog generation, it translates Verilog files to an abstract syntax tree and then maps nodes to natural language with a predefined template. For Verilog repair, it uses predefined rules to generate the wrong verilog file and then pairs EDA Tool feedback with the right and wrong verilog file. For EDA Script generation, it uses existing LLM(GPT-3.5) to obtain the description of the Script. To evaluate the effectiveness of our data augmentation method, we finetune Llama2--13B and Llama2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model (ChipGPT-FT¹) has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data.

Synovial inflammation and fibrosis are important pathological changes associated with osteoarthritis (OA). Herein, we investigated if nintedanib, a drug specific for pulmonary fibrosis, plays a positive role in osteoarthritic synovial inflammation and fibrosis. We assessed the effect of nintedanib on osteoarthritic synovial inflammation and fibrosis in a mouse model of OA created by destabilization of the medial meniscus and a macrophage M1 polarization model created by stimulating RAW264.7 cells with lipopolysaccharide. Histological staining showed that daily gavage administration of nintedanib significantly alleviated articular cartilage degeneration, reduced the OARSI score, upregulated matrix metalloproteinase‐13 and downregulated collagen II expression, and significantly reduced the synovial score and synovial fibrosis in a mouse OA model. In addition, immunofluorescence staining showed that nintedanib significantly decreased the number of M1 macrophages in the synovium of a mouse model of OA. In vitro results showed that nintedanib downregulated the phosphorylation levels of ERK, JNK, p38, PI3K, and AKT while inhibiting the expression of macrophage M1 polarization marker proteins (CD86, CD80, and iNOS). In conclusion, this study suggests that nintedanib is a potential candidate for OA treatment. The mechanisms of action of nintedanib include the inhibition of M1 polarization in OA synovial macrophages via the MAPK/PI3K‐AKT pathway, inhibition of synovial inflammation and fibrosis, and reduction of articular cartilage degeneration.

Recent advances in large language models (LLMs) have demonstrated significant potential for automated hardware description language (HDL) code generation from high-level specifications. However, two critical challenges limit further progress in this domain: the scarcity of quality Verilog training data and the inability of current approaches to generate RTL code optimized for power, performance, and area (PPA) metrics. This article presents a comprehensive data-centric framework that addresses these limitations through innovations in both pre-fine-tuning data preparation and after-fine-tuning optimization strategies. In the pre-fine-tuning phase, we tackle the data scarcity problem with an automated design-data augmentation framework that generates high-volume, high-quality natural language specifications aligned with corresponding Verilog code and EDA scripts. Our approach creates a complete RTL-level feedback loop by augmenting EDA scripts, RTL code, and EDA tool feedback. In the after-fine-tuning phase, we focus on generating PPA-aware RTL code through a novel search and prompt framework. Our approach implements iterative filtering and selection of LLM-generated Verilog variants while providing high-quality predefined prompts, including composition and interface specifications. To evaluate the effectiveness of our data augmentation method, we fine-tune Llama 2-13B and Llama 2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data. Additionally, to evaluate the effectiveness of the our agent framework, we compare the PPA on the GPT-3.5, where the results show that the agent refined RTL code can have a better quality than the generated RTL code only with GPT-3.5.

Photo-realistic rendering in XR applications using algorithms such as 3D Gaussian Splatting has been a bottleneck for real-time performance. GPUs do not provide efficient rendering, and most dedicated accelerators focus on single-object rendering, while nearly all XR scenarios involve multiple objects. We introduce ScaleGS , an algorithm-architecture co-design system designed to close the gap between real-time 3D Gaussian Splatting to real-time XR rendering. Specifically, we focus on multi-object rendering, structuring the XR rendering pipeline from an object-centric perspective and distinguishing static objects from moving ones to reduce unnecessary computations. Importantly, we identify multiple levels of parallelism across different objects and stages within the rendering pipeline, as well as high data reuse between objects within the render stage. Leveraging these insights, our acceleration framework comprises a runtime system, a micro-instruction scheduler, and a hardware accelerator. Extensive evaluations demonstrate that ScaleGS achieves comparable rendering quality to state-of-the-art dedicated 3D Gaussian Splatting accelerators, while improving throughput by 1.35× -2.14× compared with state-of-the-art rendering accelerators. ¹

This is a corrigendum for the article “A data-centric chip design agent framework for Verilog code generation” published in ACM Trans. Des. Autom. Electron Syst. 30, 6, Article 93 (October 2025), 27 pages.