In a traditional quasi-resonant (QR) control flyback converter, the switching frequency of the system will increase with the decrease of the load, so the switching loss under the light load becomes high, which greatly affects the average efficiency of the system in the whole load range. An improved QR control method called valley skip (VS) control can reduce the switching loss by decreasing the frequency of the system under the light load. However, the switching frequency of the conventional VS controller may change suddenly at some load points, and this sudden frequency hopping causes serious audible noise in the transformer. In this article, we propose a valley-locking control scheme to overcome the shortcomings of the traditional VS control technology. It can eliminate the audio noise caused by the frequency hopping in VS control. In order to verify the feasibility of the proposed method, a controller IC is fabricated with the proposed method and tested by a prototype experimental board of 24 W/12 V.

In the physical design of VLSI circuits, the congestion generated in placement stage tends to enlarge the total wirelength (TWL) and further worsens the timing and routability. In this letter, a local congestion elimination technique is proposed which can be compatible with available commercial P&R EDA tools. Driven by overflow value, the optimal keepout margins being added around the highest pin cells in specific congestion regions are searched using simulated annealing (SA) algorithm and ant colony optimization (ACO) algorithm respectively to ameliorate local congestion. Experimental results have shown that the proposed technique can reduce the design rule violations (DRV), shorts and TWL significantly.

Agentic chip design combines large language models with electronic design automation (EDA) tools to plan, execute, and revise design operations. Its effectiveness depends on how an agent translates requirements into executable tasks, interprets diagnostic information, and coordinates changes across design stages. This survey examines these relationships across digital design, agent architectures, EDA algorithm and tool development, and evaluation, with additional coverage of analog, mixed-signal, and radio-frequency applications. We compare agentic chip-design methods through the design representations they modify, the feedback used to select revisions, and the procedures used to check correctness and implementation quality. The analysis shows that broader agent control over designs and EDA software expands optimization opportunities while increasing the need to manage dependencies and verify changes across the design flow. We also compare benchmarks and evaluation methods, focusing on functional correctness, implementation quality, and computational cost. These comparisons identify research directions in specification interpretation, failure diagnosis, repository-level integration, cross-stage optimization, and efficient tool use. By synthesizing these findings, this survey aims to guide the research community in developing and evaluating more reliable and efficient chip-design agents.

This paper proposes OpenPARF, an open-source placement and routing framework for large-scale FPGA designs. OpenPARF is implemented with the deep learning toolkit PyTorch and supports massive parallelization on GPU. The framework proposes a novel asymmetric multi-electrostatic field system to solve FPGA placement. It considers fine-grained routing resources inside configurable logic blocks (CLBs) for FPGA routing and supports large-scale irregular routing resource graphs. Experimental results on ISPD 2016 and ISPD 2017 FPGA contest benchmarks and industrial benchmarks demonstrate that OpenPARF can achieve 0.4-12.7% improvement in routed wirelength and more than $2\times$ speedup in placement. We believe that OpenPARF can pave the road for developing FPGA physical design engines and stimulate further research on related topics.