Transistor-level design is pivotal for the accurate evaluation of FPGA architectures. Since traditional linear models are increasingly inadequate in advanced technology nodes, simulation-driven approaches have become the standard for FPGA architecture exploration. However, due to the non-analytical nature of delay measurements from simulations, the transistor sizing process becomes a black-box optimization problem. COFFE2 [1], [2], the state-of-the-art academic sizing tool employs a division-based brute-force approach, which is relatively time-consuming and may lose optimal solutions. In this paper, we propose a two-phase transistor sizing methodology and enhance the COFFE2 framework with Bayesian Optimization, which is well-suited for black-box optimization problems. Our proposed approach not only achieves a 11.7% improvement in the quality of results but also reduces runtime by ~40%-70%. Through extensive benchmarking on a complete design flow, from transistor-level sizing to routing with VTR benchmarks, we demonstrate that FPGA architectures optimized by our approach offer an 11.0% reduction in the area-delay product, proving the efficacy of our method.

Field-programmable gate arrays (FPGAs) have been an efficient alternative for the implementation of digital circuits. Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the LUT input number to improve performance and logic capacity will introduce exponential area overhead, substantial research has focused on designing more efficient logic architecture. Previous approaches primarily design dedicated hardware by analyzing the frequency distribution of Boolean functions and implementing those with high frequency. However, these approaches face scalability challenges due to the explosive growth in the function space. In this article, we consider the topology of cuts rather than Boolean functions they represent. By identifying topologies that occur commonly in cuts and integrating them with LUTs, we propose a new 8-input PLB architecture, named FLAIC. This architecture incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8-LUT. Post-synthesis results on VTR and Koios benchmarks demonstrate that FLAIC reduces the logic levels by over 20% compared to 6-LUTs. Additionally, post-implementation results show improvement in critical path delay by 11.9% and reduction in the number of Configurable Logic Blocks by 1.5% without sacrificing routability, compared to Intel Stratix 10-like architecture