Owing to its superior material and electrical properties such as wide bandgap and high breakdown electric field, 4H-silicon carbide (4H-SiC) has shown promise in high power, high temperature, and radiation prone environments. After success in silicon-based technology, metal–insulator–semiconductor (MIS) devices seem to be the obvious choice for 4H-SiC technology as well, due to the availability of its native insulated oxide (SiO₂). However, the use of SiO₂ in 4H-SiC technologies is not an ideal choice due to the poor quality of the SiO₂/4H-SiC interface and the low dielectric constant of SiO₂, which compromise the performance of 4H-SiC devices under high electric fields. Therefore, to exploit the superior properties of 4H-SiC, substantial efforts are being made to overcome this issue by using high-κ dielectrics such as Al₂O₃, AlN, HfO₂, Ta₂O₅, Y₂O₃, ZrO₂, TiO₂, CeO₂, and their combinations in layered stacks. This paper assesses the current status of these dielectrics and their processing in terms of types of dielectric (and their stacks), pre-deposition treatments, deposition methods, post-deposition treatments, and their viability in actual devices. Based on an extensive survey of the structural, electrical, and interfacial characteristics, a future perspective of high-κ dielectrics on 4H-SiC devices is provided.

Nowadays, we see more and more cyber-attacks on major Internet sites and enterprise networks. Intrusion Detection System (IDS) is a critical component of such infrastructure defense mechanism. IDS monitors and analyzes networks' activities for potential intrusions and security attacks. Machine-learning (ML) models have been well accepted for signature-based IDSs due to their learn ability and flexibility. However, the performance of existing IDSs does not seem to be satisfactory due to the rapid evolution of sophisticated cyber threats in recent decades. Moreover, the volumes of data to be analyzed are beyond the ability of commonly used computer software and hardware tools. They are not only large in scale but fast in/out in terms of velocity. In big data IDS, the one must find an efficient way to reduce the size of data dimensions and volumes. In this paper, we propose novel feature selection methods, namely, RF-FSR (Random Forest-Forward Selection Ranking) and RF-BER (Random Forest-Backward Elimination Ranking). The features selected by the proposed methods were tested and compared with three of the most well-known feature sets in the IDS literature. The experimental results showed that the selected features by the proposed methods effectively improved their detection rate and false-positive rate, achieving 99.8% and 0.001% on well-known KDD-99 dataset, respectively.

The degraded performance of 4H-SiC transistors due to a high density of the SiC/SiO ₂ interface states (D _IT ) (~10 ¹² -10 ¹³ eV ^-1 cm ^-2 ) has gained increasing attention in recent years. A significant amount of research is being done to improve the fabrication process of 4H-SiC devices to achieve a good quality interface, thereby reducing D _IT to an acceptable value. This paper analyzes the current passivation schemes and their effectiveness in lowering D _IT and potentially improving the performance of 4H-SiC metal-oxide-semiconductor-based devices and bipolar junction transistors. This paper also discusses the processes that affect the interface quality, such as surface preparation, oxidation methods, postoxidation annealing conditions, and other processes, such as the use of alternative dielectrics. The possibility of substantially improving the interface quality by combining some of these processes is also examined.

4H-silicon carbide (SiC)-based bipolar integrated circuits (ICs) are suitable alternatives to silicon (Si)-based ICs in high temperature applications, owing to superior properties of 4H-SiC and the robust performance of SiC bipolar junction transistors (BJTs). However, cost, size, and manufacturability of 4H-SiC ICs remains inferior to the prevalent Si-based ICs, due to large footprint and high number of epilayers in conventional SiC BJTs. An alternative to overcome these limitations is to use lateral BJTs (LBJTs). Though Si LBJTs have been demonstrated, this is the first time they are explored in 4H-SiC. This paper proposes a symmetric, self-aligned 4H-SiC LBJT design, which is relatively easier and cheaper to manufacture, has fewer epilayers, and is >90% smaller than existing structures. Extensive device simulations and optimization is performed to achieve optimal current gains, at a range of temperatures (27 °C-500 °C). The results suggest current gains of over 100 in devices with base width of 1 μm, at room temperature. The applicability of the structure is validated by designing a 4H-SiC LBJT-based emitter-coupled logic inverter, which shows stable operation and good speeds (~3 ns) up to 500 °C, while having high integration density and lower cost.