Tulika Mitra

Tulika Mitra

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Tulika Mitra

School of Computing, National University of Singapore, Singapore

Research Focus & Metrics

Academic Career Length

32Years (1995-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 April 2008 in ACM Transactions on Embedded Computing Systems
Verified
Journal Article
Open access
RWReinhard Wilhelm
Reinhard Wilhelm
JEJakob Engblom
Jakob Engblom
AEAndreas Ermedahl
Andreas Ermedahl
NHNiklas Holsti
Niklas Holsti
STStephan Thesing
Stephan Thesing
PSPer Stenström
Per Stenström
The determination of upper bounds on execution times, commonly called worst-case execution times (WCETs), is a necessary step in the development and validation process for hard real-time systems. This problem is hard if the underlying processor architecture has components, such as caches, pipelines, branch prediction, and other speculative components. This article describes different approaches to this problem and surveys several commercially available tools 1 and research prototypes.

18 June 2017
Verified
Conference Paper
Open access
MKManupa Karunaratne
Manupa Karunaratne
AMAditi Kulkarni Mohite
Aditi Kulkarni Mohite
TMTulika Mitra
Tulika Mitra
LPLi-Shiuan Peh
Li-Shiuan Peh
CGRAs are promising as accelerators due to their improved energy-efficiency compared to FPGAs. Existing CGRAs support reconfigurability for operations, but not communications because of the static neighbor-to-neighbor interconnect, leading to both performance loss and increased complexity of the compiler. In this paper, we introduce HyCUBE, a novel CGRA architecture with a reconfigurable interconnect providing single-cycle communications between distant FUs, resulting in a new formulation of the application mapping problem that leads to the design of an efficient compiler. HyCUBE achieves 1.5X and 3X better performance-per-watt compared to a CGRA with standard NoC and a CGRA with neighbor-to-neighbor connectivity, respectively.

11 October 2007 in Science of Computer Programming
Verified
Journal Article
Closed access
XLXianfeng Li
Xianfeng Li
YLYun Liang
Yun Liang
TMTulika Mitra
Tulika Mitra
ARAbhik Roychoudhury
Abhik Roychoudhury

29 May 2013
Verified
Conference Paper
Open access
PDF file
TMThannirmalai Somu Muthukaruppan
Thannirmalai Somu Muthukaruppan
MPMihai Pricopi
Mihai Pricopi
VVVanchinathan Venkataramani
Vanchinathan Venkataramani
TMTulika Mitra
Tulika Mitra
SVSanjay Vishin
Sanjay Vishin

30 September 2019 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
SWSiqi Wang
Siqi Wang
GAGayathri Ananthanarayanan
Gayathri Ananthanarayanan
YZYifan Zeng
Yifan Zeng
NGNeeraj Goel
Neeraj Goel
APAnuj Pathania
Anuj Pathania
TMTulika Mitra
Tulika Mitra
IoT Edge intelligence requires Convolutional Neural Network (CNN) inference to take place in the edge devices itself. ARM big.LITTLE architecture is at the heart of prevalent commercial edge devices. It comprises of single-ISA heterogeneous cores grouped into multiple homogeneous clusters that enable power and performance trade-offs. All cores are expected to be simultaneously employed in inference to attain maximal throughput. However, high communication overhead involved in parallelization of computations from convolution kernels across clusters is detrimental to throughput. We present an alternative framework called Pipe-it that employs pipelined design to split convolutional layers across clusters while limiting parallelization of their respective kernels to the assigned cluster. We develop a performance-prediction model that utilizes only the convolutional layer descriptors to predict the execution time of each layer individually on all permitted core configurations (type and count). Pipe-it then exploits the predictions to create a balanced pipeline using an efficient design space exploration algorithm. Pipe-it on average results in a 39% higher throughput than the highest antecedent throughput.