In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL). Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc. In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems. The performance and accuracy of a DNN is a way better than human intelligence in certain situations. However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations. Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms. Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms. This paper brings forward the various research works carried out on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators. The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN. A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed. Finally, future research and development directions are discussed, such as future trends in DNN implementation on specialized hardware accelerators. This review article is intended to serve as a guide for hardware architectures for accelerating and improving the effectiveness of deep learning research.

Photoplethysmogram (PPG) is a bio-optical technology used heavily in wearable health devices for monitoring vital sign parameters. Therefore, ensuring the quality of PPG signals is crucial for accurate measurements, as these signals are susceptible to various artifacts and noises. This article proposes a derivative-based PPG (dPPG) signal quality assessment (SQA) method to distinguish high-quality data from artifact-laden signals. The proposed method includes a first-order derivative, followed by a 3-point moving average filter to smooth the high-frequency components present in the dPPG signal. Further, the smoothed dPPG signal is fed into 2, 4, and 6-layer 1D-convolutional neural networks (1D-CNN) to classify it as a clean or noisy dPPG signal. The proposed derivative-based PPG-SQA method is tested using various PPG signals collected from standard databases. The noisy PPG signals are collected from the wrist-cup (WC-PPG) database, whereas acceleration (SYN-ACCE-PPG) and random noise (SYN-RN-PPG) affected PPG signals are synthetically generated using noise-free PPG (NF-PPG) signals. We evaluate the proposed method using performance metrics like sensitivity (SE), specificity (SP), accuracy (ACC), model size (in MB), and processing time (PT). We also implemented the proposed method on the Raspberry Pi 4 (R-Pi-4) to study its real-time feasibility. The 6-layer 1D-CNN with 32 kernels using the ReLU activation function is observed to outperform the other models and existing PPG-SQA methods. The proposed method, when compared to NF signals, achieves: 99.84% of SE, 97.94% of SP, and 99.70% of ACC for WC-PPG; 99.79% of SE, 100.00% of SP, and 99.96% of ACC for SYN-RN-PPG; and 84.48% of SE, 74.63% of SP, and 78.17% of ACC for SYN-ACCE-PPG, respectively. Results demonstrate that selecting the appropriate 1D-CNN model can achieve higher SE, SP, and ACC with a lower computational load on PC-CPU and R-Pi computing platforms. Furthermore, we test the reliability and robustness of the dPPG-1D-CNN-SQA model using the unseen databases. Our model may reduce the false alarms and energy consumption of wearable healthcare devices, which have limited battery capacity and computational resources.

MmWave radars play a vital role in autonomous systems, such as unmanned aerial vehicles (UAVs), unmanned surface vehicles (USVs), ground station control and monitoring systems. The challenging task when using mmWave radars is to estimate the accurate angle of arrival (AoA) of the targets, due to the limited number of receivers. In this paper, we present a novel AoA estimation technique, using mmWave FMCW radars operating in the frequency range 77–81 GHz by utilizing the mechanical rotation. Rotating the radar also increases the field of view in both azimuth and elevation. The proposed method estimates the AoA of the targets, using only a single transmitter and receiver. The measurements are carried out in a variety of practical scenarios including pedestrians, a car, and an UAV, also known as a drone. With measured data, range-angle maps are created, and morphological operators are used to estimate the AoA of the targets. We also process radar range-angle images for improved visual representation. The proposed method will be extremely beneficial for practical ground stations, traffic control and monitoring frameworks for both on-ground and airborne vehicles.

Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: Dynamically Reconfigurable Resource Array (DRRA) and Distributed Memory Architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors α and β so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method.

State-of-the-art modern microprocessor and domain-specific accelerator designs are dominated by data-paths composed of regular structures, also known as bit-slices. Random logic placement and routing techniques may not result in an optimal layout for these data-path-dominated designs. As a result, implementation tools such as Cadence’s Innovus include a Structured Data-Path (SDP) feature that allows data-path placement to be completely customized by constraining the placement engine. A relative placement file is used to provide these constraints to the tool. However, the tool neither extracts nor automatically places the regular data-path structures. In other words, the relative placement file is not automatically generated. In this paper, we propose a semi-automated method for extracting bit-slices from the Innovus SDP flow. It has been demonstrated that the proposed method results in 17% less density or use for a pixel buffer design. At the same time, the other performance metrics are unchanged when compared to the traditional place and route flow.