International audienceMost Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. This design decision leads to buffer underutilization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage for performance and energy gains, we present a synchronous and elastic buffer implementation of a router architecture called Roundabout with intrinsic resource sharing. Roundabout is inspired by real-life traffic roundabouts and consists of lanes shared by multiple input and output ports. Roundabout offers performance improvement of 61% for uniform traffic pattern and up to 88% for non-uniform traffic pattern over the Hermes router, a typical input buffered router. In terms of power, it consumes 24% less than the Hermes router. Roundabout provides a highly parametric architecture that can produce different router configurations with varying topological trade-offs for performance gains without sacrificing area

Network-on-Chip provides scalable communication in Systems-on-Chip with many Intellectual Property cores. Studies have shown that unutilized router buffers lead to significant network performance degradation. This work presents Roundabout, a new asynchronous router architecture with inherent and effective buffer utilization. Inspired by real-life multi-lane roundabouts, it consists of lanes shared by input and output ports. A prototype of Roundabout is evaluated using 45nm CMOS technology. The router is able to achieve a throughput of 465 Mflit/sec. It achieves a network saturation threshold of 129 Gbps on a 4x4 Mesh topology network. Roundabout performance, area and power results are competitive with existing synchronous and asynchronous solutions. It provides good topological tradeoffs for significantly improving network performance without corresponding area overhead.

Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems. A typical NoC router is made up of buffers used to store packets that are unable to advance to their desired destination. However, buffers consume significant power/area and are often underutilized, especially in cases of applications with non-uniform traffic patterns thus leading to performance degradation for such applications. To improve network performance, the Roundabout NoC (R-NoC) concept is considered. R-NoC is inspired by real-life multi-lane traffic roundabouts and consists of lanes that are shared by multiple input/output ports to maximize buffering resource utilization. R-NoC relies on router-internal adaptive routing that decides the lane path based on back pressure. Back pressure makes it possible to assess lane utilization and route packets accordingly. This is made possible thanks to the use of elastic buffers for control flow, a clever type of handshaking in a way similar to asynchronous circuits. Another prominent feature of R-NoC is that internal routing and arbitration are completely distributed which allows for significant freedom in deciding internal router topology and parameters. This work leverages this property and proposes novel yet unexplored configurations for which an in-depth evaluation of corresponding implementations on 45 nm CMOS technology is given. Each configuration is evaluated performance and power-wise on both synthetic and real application traffic. Several R-NoC configurations are identified and demonstrated to provide very significant performance improvements over standard mesh configurations and a typical input-buffered router, without compromising area and power consumption. Exploiting the distributed nature of R-NoC routers, a diagonally-linked configuration is then proposed which incurs moderate area overhead and features yet better performance and energy efficiency.

With technological advances, significant changes are taking place in automotive domain. Modern automobile combines functionalities ranging from safety critical functions such as control systems for engine to navigation and infotainment. To meet the performances requirements of these systems, automotive industry is shifting to multi-core systems. This increases the design complexity. Efficient and fast design space exploration frameworks are required to deal with this design complexity. This paper presents a framework for exploring automotive application design on multi-core systems. It considers an automotive-specific application modeling language named Amalthea and a distributed-memory multi-core system architecture for execution. The effectiveness of our framework is shown on an engine control application.

Adaptive techniques, such as adaptive task migration at runtime, have been introduced in Multiprocessor Systems-on-Chip in order to optimize performance and power consumption. Nevertheless, there is also a potential to adapt the MPSoC communication architecture for further performance and power benefits. As an example, adaptive routings in Networks-on-Chip (NoCs) have been exploited for performance gains. Another promising opportunity, which is here explored, is the adaptive use of the buffering resources in the NoC router. This work presents Roundabout, a new NoC router architecture with inherent and effective buffer utilization. Inspired by real-life multi-lane roundabouts, it consists of lanes shared by input and output ports. A prototype of Roundabout is evaluated using 45nm CMOS technology. The router is able to achieve a throughput of 465 Mflit/sec and without significant area overhead. It achieves a network saturation threshold of 68Gbps on a 4×4 Mesh topology network.

Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.