IP piracy, reverse engineering, and tampering with FPGA based IP is increasing over time. ROPUF based IP obfuscation can provide a feasible solution. In this paper, a novel approach of FPGA IP obfuscation is implemented using Ring Oscillator based Physical Unclonable Function (ROPUF) and random logic gates. This approach provides a lock and key mechanism as well as authentication of FPGA based designs to protect from security threats. Using the Xilinx ISE design tools and ISCAS 89 benchmarks we have designed a secure FPGA based IP protection scheme with an average of 15% area and 10% of power overhead.

Reverse engineering process serves essential functions in software analysis and security auditing and malware detection but requires significant time and effort. Researchers and practitioners now investigate how Artificial Intelligence (AI) technology can automate and improve different reverse engineering procedures. This survey provides an extensive evaluation of recent AI-based reverse engineering techniques which focus on software decompilation and function identification as well as control flow recovery and vulnerability analysis. The paper presents a classification system for existing methods while comparing them through an analysis of their development from traditional rule-based systems to contemporary deep learning frameworks. The research examines fundamental datasets together with field tools and evaluation metrics. This paper establishes a fundamental understanding of AI integration in reverse engineering for software security while discussing future development directions.

Smart grid (SG) has evolved as a recent topic of discussion and research globally, due to the integration of communication and internet in its network. It facilitates the bidirectional flow of information and power making it vulnerable to attacks including denial of service, fault injection, man-in-the-middle, etc. An integral part of the SG, is the advanced metering infrastructure (AMI), which in turn embodies within itself a critical component of SG such as smart meter (SM), utility company (UC), etc. The AMI also exchanging data and electricity within itself, is a gold mine for adversaries. In addition, the smart meter, being a hardware entity, is susceptible to hardware oriented attacks. In this work, a novel authentication scheme, ZEBRA, for the AMI is proposed. ZEBRA utilizes a combination of Ring Oscillator Physical Unclonable Functions (ROPUFs) for authentication and blockchain for traceability in a Zero Trust Architecture (ZTA) to enhance the security of the AMI. The architecture entails a design that allows for the smart meters in the AMI network to be retrofitted with the new hardware and does not require any use of onboard memory. The authentication scheme, itself, is built to function using the Hamming code parity bits of the ROPUF’s response, rather than the direct responses from the ROPUFs. This ensures a higher degree of difficulty towards a malicious actor attempting to hack the device. By combining ROPUFs and blockchain technology for ZTA a maximum security, real-time AMI authentication scheme is realized. The investigation aimed at satisfying the tenets of ZTA laid down by National Institute of Standard and Technology. ROPUF and blockchain have been used individually and together to realize these tenets for sucessful implementation of ZEBRA.

Ring Oscillator Physical Unclonable Function (ROPUF) has been the preferred choice for embedding hardware-oriented security and trust in FPGA based systems. Parameters such as uniformity, uniqueness, bit-aliasing, and reliability have been used to measure the performance of PUFs. In this paper, we present an XOR-Inverter based ROPUF which has improved uniformity, uniqueness, and bit-aliasing when compared with other designs. From the results, it is observed that the proposed 3 stage XOR-Inverter based design can produce Challenge Response Pairs (CRPs) with 47.64% uniqueness (50% ideal value), 49.8% uniformity (50% ideal value), and 50% bit-aliasing (50% ideal value) when compared to the best results from other similar ROPUF structures which yield uniqueness, uniformity, and bit-aliasing of 45%–47%, 50.53% and 47–50.5%, respectively. The reliability of our proposed PUF is better than most existing designs; however, it is fractionally less than that of the design presented in [6].

The proliferation of Internet of Things (IoT) devices and distributed computing environments has intensified the demand for robust, adaptive security frameworks capable of continuous trust evaluation. Traditional perimeter-based security models fail to address the dynamic nature of modern network ecosystems, where device behavior evolves continuously and adversarial threats adapt in real-time. This paper introduces Adaptive-AI-ZeroTrust-Chain (AAZTC), a novel framework that integrates artificial intelligence-driven dynamic trust boundary modeling with blockchain-based verifiable access logging to enable granular, auditable zero-trust enforcement. The proposed architecture employs deep reinforcement learning algorithms for continuous behavioral analysis and trust score computation, while leveraging smart contracts on a permissioned blockchain to ensure immutable, transparent access decision records. The framework incorporates a lightweight post-quantum cryptographic module to future-proof security against emerging quantum computing threats. Extensive experiments conducted on the NSL-KDD and CICIDS2017 datasets demonstrate that AAZTC achieves 98.73% detection accuracy, 97.89% precision, and 98.21% F1-score, outperforming state-of-the-art baseline methods by margins of 3.2–5.8%. The system maintains low latency characteristics with average trust decision times of 12.4 ms, making it suitable for real-time IoT deployments. Ablation studies confirm the synergistic contributions of each architectural component, validating the comprehensive design philosophy underlying AAZTC.

Hardware oriented security attacks, IP theft, and information reliability have become serious issues in modern day world. Numerous techniques have been developed for protecting hardware systems from malicious attacks. Ring Oscillator Physical Unclonable Function (ROPUF) is one of the favored choices for hardware-oriented security. ROPUFs are implemented in microelectronic circuits including Field Programmable Gate Arrays (FPGAs) to generate unique secret keys that are unclonable on any other device. The strength and performance of Physical Unclonable Functions (PUFs) are measured through parameters like reliability, uniqueness, uniformity, randomness, and bit-aliasing. In this paper, we analyze the performance of an AND-Inverter based ROPUF which shows performance improvement over previous designs. Three, five, and seven stage AND-Inverter ROPUFs are implemented for a comparative study of their performance metrics. It is found that the 3-stage AND-Inverter ROPUF has better uniqueness (47.5%), and ideal bit-aliasing (50%). The 7-stage AND-Inverter ROPUF has the best uniformity (50.07%) and ideal bit aliasing (50%). However, the AND-Inverter based ROPUFs perform poorly in terms of reliability.