Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 10¹⁸ calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community.

Chalcogenide materials are receiving increasing interest for their many applications as active materials in emerging memories, such as phase-change memories, programmable metallization cells, and cross-point devices. The great advantage of these materials is the capability to appear in two different phases, the amorphous and the crystalline phases, with rather different electrical properties. The aim of this work is to provide a physically based model for conduction in the amorphous chalcogenide material, able to predict the current-voltage $\left(I-V\right)$ characteristics as a function of phase state, temperature, and cell geometry. First, the trap-limited transport at relatively low currents (subthreshold regime) is studied, leading to a comprehensive model for subthreshold conduction accounting for (a) the shape of the $I-V$ characteristics, (b) the measured temperature dependence, (c) the dependence of subthreshold slope on the thickness of the amorphous phase, and (d) the voltage dependence of the activation energy. The threshold switching mechanism is then explained by the nonequilibrium population in high-mobility shallow traps at high electric field and by the nonuniform field distribution along the amorphous layer thickness. A single analytical model is then shown which is able to account for subthreshold conduction, threshold switching, negative differential resistance region, and ON regime. The model can be applied for fast yet physically based computation of the current in chalcogenide-based devices (e.g., phase change memory cells and arrays) as a function of applied voltage, temperature, and programmed state.

Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.