Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

This research paper presents the effect of working temperature on the I ON , I OFF and I ON /I OFF ratio of gate all around nanowire TFET. The (Silvaco) simulation tool has been used to investigate the temperature characteristics of a transistor. The working temperature range of this study is from -50 to 150 step-up 25 °C. The final results indicate that the negative effects of increasing working temperature of gate all around nanowire TFET due to decreasing of the I ON /I OFF ratio. Hence, the results for I ON /I OFF ratio vs. working temperature characteristics may lead to the use of TFET in electronic circuits with lowest possible working temperature to obtain higher I ON /I OFF ratio.

Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

This paper aims to enhance the performance of the High Electron Mobility Transistor (HEMT) according to downscaling dimensions based on the electrical properties and semiconductor materials (GaN, Si3N4, ALGaN and Si). This is to solve difficulties with reducing dimensions and ensuring HEMT has the highest performance possible. This goal was met when the physical scaling restrictions of channel diameters for different HEMTs were concurrently shrunk without compromising their performance. A simula-tion study was done using four variable factors (length, width, of the channel and length, width of the source and drain). Three electrical characteristics were used to assess the impact of altering dimensions on the performance of each kind of HEMT: threshold voltage Vt, ON-state/OFF-state current (ION/IOFF) ratio, and transconductance gm. To conduct experimental simulations under the specified situation, the well-known Silvaco TCAD simulation tool was used. The acquired simulation results revealed that the optimum performance for the downscaling device was achieved at the channel length of 1.6μm, the channel width of 0.3μm, the length of source and drain is 0.4μm and finally the width of source and drain is 0.05 μm.

The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower work function in drain (ϕ=3.90 eV) to induce electron charges. Many electrical characterizations in this paper are considered to study the performance of this device like a current drain (ID) versus voltage gate (Vgs), ION/IOFF ratio, threshold voltage (VT) transconductance (gm), and sub-threshold swing (SS). The signification of this paper comes into view enhancement the performance of the device. Results show that high dielectric (K=12), oxide thickness (Tox=1 nm), channel length (Lch=42 nm), and higher work function for the gate (ϕ=4.5 eV) tend to best charge plasma silicon tunnel field-effect transistor characterization.

This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.