Pt100 is a resistance temperature detector characterized by a relatively linear resistance/temperature relationship in a narrow temperature range. However, the Pt100 sensor shows a certain degree of static transfer function nonlinearity of 4.42 % in the range between −200 °C and 850 °C, which is unacceptable for some applications. As a solution to this problem, a mixed-mode linearization method based on a special dual-stage piecewise linear ADC design is proposed in this paper. The first stage of the proposed dual-stage piecewise linear ADC is performed with a low-complex and low-power flash ADC of a novel sequential design. The novelty of the proposed sequential design is reflected in the fact that the number of employed comparators is equal to the flash ADC resolution. The second stage is performed with a delta-sigma ADC with a differential input and differential reference. Using the 6-bit flash ADC of novel design and the 24-bit delta-sigma ADC, the nonlinearity error is reduced to 2.6·10⁻³ %, in the range between −200 °C and 850 °C. Two more ranges are examined, and the following results are obtained: in the range between 0 °C and 500 °C, the nonlinearity error is reduced from 1.99 % to 5·10⁻⁴ %, while in the range between −50 °C and 150 °C, the nonlinearity error is reduced from 0.755 % to 2.15·10⁻⁴ %.

Optical rotary encoders generate nonlinear sine and cosine signals in response to a change of angular position that is being measured. Due to the nonlinear shape of encoder output signals, encoder sensitivity to very small changes of angular position is low, causing a poor measurement accuracy level. To improve the optical encoder sensitivity and to increase its accuracy, an improved linearization circuit based on pseudo-linear signal generation and its further linearization with the two-stage piecewise linear analog-to-digital converter is presented in this paper. The proposed linearization circuit is composed of a mixed-signal circuit, which generates analog pseudo-linear signal and determines the first four bits of the final digital result, and the two-stage piecewise linear analog-to-digital converter, which performs simultaneous linearization and digitalization of the pseudo-linear signal. As a result, the maximal value of the absolute measurement error equals to 3.77168·10⁻⁵ [rad] (0.00216°) over the full measurement range of 2π [rad].

A cost-effective method for resolution increase of a two-stage piecewise linear analog-to-digital converter used for sensor linearization is proposed in this paper. In both conversion stages flash analog-to-digital converters are employed. Resolution increase by one bit per conversion stage is performed by introducing one additional comparator in front of each of two flash analog-to-digital converters, while the converters’ resolutions remain the same. As a result, the number of employed comparators, as well as the circuit complexity and the power consumption originating from employed comparators are for almost 50 % lower in comparison to the same parameters referring to the linearization circuit of the conventional design and of the same resolution. Since the number of employed comparators is significantly reduced according to the proposed method, special modifications of the linearization circuit are needed in order to properly adjust reference voltages of employed comparators.

This paper proposes a compact two-stage analog-to-digital converter (ADC), leveraging a nonuniform flash ADC to address sensor linearization challenges. The proposed approach reduces circuit complexity in conventional two-stage linearizing ADCs while preserving overall resolution and effective nonlinearity reduction. The compactness of the proposed two-stage ADC is achieved by reducing the number of comparators in the nonuniform flash ADC and reusing the same flash ADC across both conversion stages. Consequently, the total number of comparators is reduced by nearly 75%, while the number of resistors is reduced by 50% compared to a conventional two-stage ADC having the identical resolutions in both stages as the proposed architecture. Nonuniform quantization is implemented using a reference resistor ladder with different resistance values, generating quantization levels that approximate the inverse of the nonlinear input signal and perform linearization. Performance of the proposed two-stage ADC is evaluated through LabVIEW simulations using a Negative Temperature Coefficient (NTC) thermistor (Vishay NTCLE428E3103F400L) as a case study. Results demonstrate a reduction in measurement error from 1 °C to 0.0033 °C in the range from −20 °C to 60 °C, achieving an overall resolution of 20 bits using a 10-bit nonuniform flash ADC.

This paper presents a method for the nonlinearity compensation of an optical rotary encoder. The proposed method is based on the application of 1) a special 4-bit mixed analog-digital circuit used for the generation of a quasi-linear signal, and 2) a two-stage nonlinear ADC which performs linearization and digital conversion of the quasi-linear signal at the same time. The quasi-linear signal is obtained by combining fragments of phase-shifted sinusoidal signals, where each fragment is presented with a 4-bit digital code. In the continuation, the quasi-linear signal is linearized with the two-stage nonlinear ADC of a compact design based on the application of a single flash ADC in both conversion stages. Additionally, the design of the flash ADC is modified so that the number of employed comparators is equal to the resolution of the flash ADC. For instance, by linearizing an optical rotary encoder using the 4-bit mixed analog-digital circuit and the 20-bit two-stage nonlinear ADC containing 10 comparators, the maximal value of the absolute measurement error can be reduced to 3.23·10-5°.