Emerging on-chip communication technologies like wireless Networks-on-Chip (WiNoCs) have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. This paper presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance, power, and reliability requirements demanded by the next generation of manycore architectures. Recently, emerging on-chip communication technologies, like wireless Networks-on-Chip (WiNoCs), have been proposed as candidate solutions for addressing the scalability limitations of conventional multi-hop NoC architectures. In a WiNoC, a subset of network nodes are equipped with a wireless interface which allows them long-range communication in a single hop. Assessing the performance and power figures of NoC and WiNoC architectures requires the availability of simulation tools that are often limited on modeling specific network configurations. This article presents Noxim, an open, configurable, extendible, cycle-accurate NoC simulator developed in SystemC, which allows to analyze the performance and power figures of both conventional wired NoC and emerging WiNoC architectures.

Machine learning techniques, particularly those based on neural networks, are always more often used at the edge of the network by IoT nodes. Unfortunately, the computation capabilities demanded by those applications, together with their energy efficiency related constraints, exceed those exposed by embedded general-purpose processors. For this reason, the use of domain-specific hardware accelerators is considered the most viable solution to the unsustainable “Turing tariff” of general-purpose hardware. Starting from the observation that memory and communication traffic account for a large fraction of the overall latency and energy in deep neural network (DNN) inferences, this paper proposes a new compression technique aimed at (i) reducing the memory footprint for storing the model parameters of a DNN, and (ii) improving DNN inference latency and energy on resource-constrained IoT devices. The proposed compression technique, namely, LineCompress, is applied on a set of representative convolutional neural networks (CNNs) for object recognition mapped on a state-of-the-art domain-specific hardware accelerator targeted for resource-constrained IoT devices. We show that, on average, 7.4× memory footprint reduction can be obtained, thus reducing the memory and communication traffic that result to 77% and 87% inference latency and energy reduction, respectively, trading-off efficiency vs. accuracy.

Wireless Network-on-Chip (WiNoC) represents a promising emerging communication technology for addressing the scalability limitations of future manycore architectures. In a WiNoC, high-latency and power-hungry long-range multi-hop communications can be realized by performance- and energy-efficient single-hop wireless communications. However, the energy contribution of such wireless communication accounts for a significant fraction of the overall communication energy budget. This article presents a novel energy managing technique for WiNoC architectures aimed at improving the energy efficiency of the main elements of the wireless infrastructure, namely, radio-hubs. The rationale behind the proposed technique is based on selectively turning off, for the appropriate number of cycles, all the radio-hubs that are not involved in the current wireless communication. The proposed energy managing technique is assessed on several network configurations under different traffic scenarios both synthetic and extracted from the execution of real applications. The obtained results show that the application of the proposed technique allows up to 25% total communication energy saving without any impact on performance and with a negligible impact on the silicon area of the radio-hub.

The wireless Network-on-Chip (WiNoC) design paradigm represents an emergent and viable solution for addressing the scalability limitations of future manycores architectures. Unfortunately, components such as the buffers and the transceiver of the radio-hubs in a WiNoC, account for a significant fraction of the total communication energy budget. In this paper, we present WIRXSleep, a mechanism aimed at improving the energy efficiency of radio-hubs in WiNoC architectures. WIRXSleep selectively and dynamically disables receiver modules and buffers of those radio-hubs that will be not involved in any communication during the next forthcoming clock cycles. Its application on different WiNoC topologies, with different configurations, and under different traffic scenarios has resulted interesting energy savings (up to 25%) without any impact on performance and with a negligible impact on cost metrics.