Maurizio Palesi

Prof. Maurizio Palesi


Research Focus & Metrics

Academic Career Length

27Years (2000-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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3 March 2008 in IEEE Transactions on Computers
Verified
Journal Article
Closed access
GAGiuseppe Ascia
Giuseppe Ascia
VCVincenzo Catania
Vincenzo Catania
MPMaurizio Palesi
Maurizio Palesi
Davide PattiDavide Patti
Davide Patti
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. A selection function is used to select the output channel where the packet will be forwarded on. In this paper we present a novel selection strategy that can be coupled with any adaptive routing algorithm. The proposed selection strategy is based on the concept of Neighbors-on-Path the aims of which is to exploit the situations of indecision occurring when the routing function returns several admissible output channels. The overall objective is to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator under traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection strategy applied to the Odd-Even routing algorithm yields an improvement in both average delay and saturation point up to 20% and 30% on average respectively, with a minimal overhead in terms of area occupation. In addition, a positive effect on total energy consumption is also observed under near-congestion packet injection rates.

13 June 2025 in ACM Computing Surveys
Verified
Journal Article
Open access
CSCristina Silvano
Cristina Silvano
DIDaniele Ielmini
Daniele Ielmini
FFFabrizio Ferrandi
Fabrizio Ferrandi
LFLeandro Fiorin
Leandro Fiorin
SCSerena Curzel
Serena Curzel
SPStefania Perri
Stefania Perri
Recent trends in deep learning (DL) have made hardware accelerators essential for various high-performance computing (HPC) applications, including image classification, computer vision, and speech recognition. This survey summarizes and classifies the most recent developments in DL accelerators, focusing on their role in meeting the performance demands of HPC applications. We explore cutting-edge approaches to DL acceleration, covering not only GPU- and TPU-based platforms but also specialized hardware such as FPGA- and ASIC-based accelerators, Neural Processing Units, open hardware RISC-V-based accelerators, and co-processors. This survey also describes accelerators leveraging emerging memory technologies and computing paradigms, including 3D-stacked Processor-In-Memory, non-volatile memories like Resistive RAM and Phase Change Memories used for in-memory computing, as well as Neuromorphic Processing Units, and Multi-Chip Module-based accelerators. Furthermore, we provide insights into emerging quantum-based accelerators and photonics. Finally, this survey categorizes the most influential architectures and technologies from recent years, offering readers a comprehensive perspective on the rapidly evolving field of deep learning acceleration.

1 October 2007 in Journal of Systems Architecture
Verified
Journal Article
Closed access
GAGiuseppe Ascia
Giuseppe Ascia
VCVincenzo Catania
Vincenzo Catania
Alessandro Di NuovoAlessandro Di Nuovo
Alessandro Di Nuovo
MPMaurizio Palesi
Maurizio Palesi
Davide PattiDavide Patti
Davide Patti

1 January 2004
Verified
Conference Paper
Open access
PDF file
GAGiuseppe Ascia
Giuseppe Ascia
VCVincenzo Catania
Vincenzo Catania
MPMaurizio Palesi
Maurizio Palesi

22 October 2006
Verified
Conference Paper
Open access
PDF file
MPMaurizio Palesi
Maurizio Palesi
RHRickard Holsmark
Rickard Holsmark
SKShashi Kumar
Shashi Kumar
VCVincenzo Catania
Vincenzo Catania
In this paper, we present a methodology to specialize the routing algorithm in routing table based NoC routers. It tries to maximize the communication performance while ensuring deadlock free routing for an application. We demonstrate through analysis that routing algorithms generated by our methodology have higher adaptiveness as compared to turn-model based deadlock free routing algorithms for a mesh topology NoC architecture. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. The routing algorithms generated by the proposed methodology achieve an improvement in delay close to 50% and 30% over deterministic XY routing algorithm and adaptive Odd-Even routing algorithm respectively.

1 October 2006
Verified
Conference Paper
Closed access
GAGiuseppe Ascia
Giuseppe Ascia
VCVincenzo Catania
Vincenzo Catania
MPMaurizio Palesi
Maurizio Palesi
Davide PattiDavide Patti
Davide Patti
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm to improve the performance with a minimal overhead on area and energy consumption. The proposed approach introduces the concept of neighbors-on-path to exploit the situations of indecision occurring when the routing function returns several admissible output channels. A selection strategy is developed with the aim to choose the channel that will allow the packet to be routed to its destination along a path that is as free as possible of congested nodes. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. Results obtained show how the proposed selection policy applied to the odd-even routing algorithm outperforms other deterministic and adaptive routing algorithms both in average delay and energy consumption