Pedro Roque

Prof. Pedro Roque

Polytechnic University of Portalegre, Portalegre, Portugal
orcid

Research Focus & Metrics

Academic Career Length

11Years (2016-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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2 October 2024 in Symmetry
Verified
Journal Article
Open access
PDF file
Sérgio Duarte CorreiaSérgio Duarte Correia
Sérgio Duarte Correia
Pedro RoquePedro Roque
Pedro Roque
João P. Matos-CarvalhoJoão P. Matos-Carvalho
João P. Matos-Carvalho
In this paper, the concept of symmetry is used to design the efficient inference of a fall-detection algorithm for elderly people on embedded processors—that is, there is a symmetric relation between the model’s structure and the memory footprint on the embedded processor. Artificial intelligence (AI) and, more particularly, Long Short-Term Memory (LSTM) neural networks are commonly used in the detection of falls in the elderly population based on acceleration measures. Nevertheless, embedded systems that may be utilized on wearable or wireless sensor networks have a hurdle due to the customarily massive dimensions of those networks. Because of this, the algorithms’ most popular implementation relies on edge or cloud computing, which raises privacy concerns and presents challenges since a lot of data need to be sent via a communication channel. The current work proposes a memory occupancy model for LSTM-type networks to pave the way to more efficient embedded implementations. Also, it offers a sensitivity analysis of the network hyper-parameters through a grid search procedure to refine the LSTM topology network under scrutiny. Lastly, it proposes a new methodology that acts over the quantization granularity for the embedded AI implementation on wearable devices. The extensive simulation results demonstrate the effectiveness and feasibility of the proposed methodology. For the embedded implementation of the LSTM for the fall-detection problem on a wearable platform, one can see that an STM8L low-power processor could support a 40-hidden-cell LSTM network with an accuracy of 96.52%.

1 November 2018
Verified
Conference Paper
Closed access
Pedro RoquePedro Roque
Pedro Roque
VPVasco Pedro
Vasco Pedro
DDDaniel Diaz
Daniel Diaz
SASalvador Abreu
Salvador Abreu
Recently, we developed the Parallel Heterogeneous Architecture Constraint Toolkit (PHACT), which is a multi-threaded constraint solver capable of using all the available devices which are compatible with OpenCL, in order to speed up the constraint satisfaction process. In this article, we introduce an evolution of PHACT which includes the ability to execute FlatZinc and MiniZinc models, as well as architectural improvements which boost the performance in solving CSPs, especially when using GPUs.

8 September 2016
Verified
Book Chapter
Closed access
Pedro RoquePedro Roque
Pedro Roque
VPVasco Pedro
Vasco Pedro
SASalvador Abreu
Salvador Abreu

27 September 2018
Verified
Book Chapter
Closed access
PDF file
Pedro RoquePedro Roque
Pedro Roque
VPVasco Pedro
Vasco Pedro