Prof. Te-Kuang Chiang

Co-authors

Following

Followers

Research Focus & Metrics

Explore full metrics on Scilit

Academic Career Length

20Years (2007-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications

26 October 2015 in Materials

Journal Article

Effects of Electrodes on the Switching Behavior of Strontium Titanate Nickelate Resistive Random Access Memory

Strontium titanate nickelate (STN) thin films on indium tin oxide (ITO)/glass substrate were synthesized using the sol-gel method for resistive random access memory (RRAM) applications. Aluminum (Al), titanium (Ti), tungsten (W), gold (Au) and platinum (Pt) were used as top electrodes in the STN-based RRAM to probe the switching behavior. The bipolar resistive switching behavior of the set and reset voltages is in opposite bias in the Al/STN/ITO and Pt/STN/ITO RRAMs, which can be partly ascribed to the different work functions of top electrodes in the ITO. Analyses of the fitting results and temperature-dependent performances showed that the Al/STN/ITO switching was mainly attributed to the absorption/release of oxygen-based functional groups, whereas the Pt/STN/ITO switching can be associated with the diffusion of metal electrode ions. The Al/STN/ITO RRAM demonstrated a high resistance ratio of >10⁶ between the high-resistance state (HRS) and the low-resistance state (LRS), as well as a retention ability of >10⁵ s. Furthermore, the Pt/STN/ITO RRAM displayed a HRS/LRS resistance ratio of >10³ and a retention ability of >10⁵ s.

28 June 2016 in IEEE Transactions on Electron Devices

Journal Article

A Short-Channel-Effect-Degraded Noise Margin Model for Junctionless Double-Gate MOSFET Working on Subthreshold CMOS Logic Gates

Te-Kuang Chiang

Based on the device and equivalent transistor model, we present a short-channel-effect (SCE)-degraded noise margin (NM) model for junctionless double-gate MOSFET working on subthreshold CMOS logic gate. The device parameters such as the thick silicon thickness, thick gate oxide thickness, high doping density, and short channel length can severely degrade the NM due to serious SCE. By contrast, both the small subthreshold slope η and the balanced transistor strength S can suppress the NM degradation more efficiently. The required minimum supply voltage Vdd,min for the subthreshold CMOS logic gate is derived by the criterion of the NM larger than thermal noise to ensure the correct logic gate operation. Being similar to drain-induced barrier lowering, allowable NM corresponding to the minimum channel length can also be uniquely controlled and determined by the scaling factor according to the scaling theory.

1 June 2007 in Japanese Journal of Applied Physics

Journal Article

A New Two-Dimensional Analytical Model for Short-Channel Symmetrical Dual-Material Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors

Te-Kuang Chiang

Mei-Li Chen

10 January 2017 in IEEE Transactions on Electron Devices

Journal Article

Effects of Ni in Strontium Titanate Nickelate Thin Films for Flexible Nonvolatile Memory Applications

Ke-Jing Lee

Yu-Chi Chang

Cheng-Jung Lee

Li-Wen Wang

Dei-Wei Chou

Yeong-Her Wang

This paper investigated the performance of flexible resistive random access memory devices based on simple spin-coated sol-gel-derived strontium titanate nickelate (STN) thin films on polyethylene terephthalate substrate. A high on/off ratio of 105 and a uniform current distribution were demonstrated. The strong bonding between bidentate ligands of nickel (II) acetylacetone and titanium metal ion enabled the chelation effect, which contributed to the stability of the STN thin film, especially for moisture resistivity. Fourier transform infrared spectroscopy analysis was utilized to examine the effects on the resistive switching behaviors after 90 days under an atmospheric environment according to the chelation effect of the STN thin films. The devices were fabricated on a flexible plastic substrate, and they exhibited excellent durability upon repeated bending tests. They demonstrated good potential application for flexible and low-cost memory devices.

4 October 2016 in IEEE Transactions on Electron Devices

Journal Article

A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

Te-Kuang Chiang

In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, such as the thick silicon thickness t _si , thick gate oxide thickness t _ox , and short channel length L _g , can severely degrade the LS and NM. On the contrary, both the small subthreshold slope η and balanced transistor strength S induced by device parameters can suppress the NM and LS degradation efficiently. The required minimum supply voltage V _dd,min for the subthreshold CMOS logic gate is derived by the criterion of the NM ≥ KT/q to ensure the correct logic gate operation. Being similar to DIBL, both NM and LS degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory. Finally, considerations on the impact of process/voltage/temperature variation are also included for NM/LS behavior analysis.

1 October 2020 in Microelectronics Journal

Journal Article

Nanosheet FET: A new subthreshold current model caused by interface-trapped-charge and its application for evaluation of subthreshold logic gate

Te-Kuang Chiang

About Me

Te-Kuang Chiang, Professor and Doctoral Supervisor of the Advanced Device Simulation Laboratory of National Kaohsiung University, LSI IC design Engineer of the United States, Senior Member of IEEE, Senior Member of the Chinese Engineering Education Association (IEET), Member of the Special Case Examination Committee of the Ministry of Science and Technology of Taiwan, and the Patent Examination Committee of Taiwan， IEEE Tainan EDS Vice President of the Chapter. Chiang Te-Kuang served as a reviewer for IEEE Trans on Electron Device， IEEE Electronic device letter， IEEE Material and device reliability， Solid-state Electronics， IEEE Trans on Nanotechnology， Journal of Microelectronics， Microelectronics Reliability， International Journal of Numerical Modeling， Semiconductor Science and Technology， Applied Physics letter， Journal of Computational Electronics， Journal of Japanese Applied Physics， IEEE Express， Micro and nanostructure etc. and other international journals and magazines. Te-Kuang Chiang specializes in the characteristic analysis, simulation and modeling of integrated circuit devices. Focus on the subthreshold behavior modeling of multiple gates（MG）field-effect transistor (FET) containing a double-gate（DG）MOSFET， Surround-gate MOSFET （SRG） MOSFET， FinFET MOSFET， Quadruple-gate (QG) MOSFET, Pi-gate （Pi-G） MOSFET. This theory was further applied to low-power and low-voltage integrated circuits. There are also many research results Published in IEEE Trans on Electron De

Prof. Te-Kuang Chiang

Prof. Te-Kuang Chiang

Research Focus & Metrics

Academic Career Length

Publication Type Breakdown

Representative Publications

About Me