This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip has been fabricated and the area overhead due to power domain separation and completion detection circuitry is 13.6%. The improvement in throughput due to asynchronous operation is 52.58%. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.

For mm-sized implants incorporating silicon integrated circuits, ensuring life-time operation of the chip within the corrosive environment of the body still remains a critical challenge. For the chips packaging, various polymeric and thin ceramic coatings have been reported, demonstrating high biocompatibility and barrier properties. Yet, for the evaluation of the final packaging and lifetime prediction, the conventional helium leak test method can no longer be used due to the mm-size of such implants. Alternatively, accelerated soak studies are typically used instead. For such studies, early detection of moisture/ion ingress using an in-situ platform may result in a better prediction of lifetime functionality. In this work, we have developed such a platform on a CMOS chip. The changes in the inter layer dielectric resistance within the chip represent the ingress, and are tracked by the implemented chip, which consists of a sensing array and an on-chip measurement engine. The measurement system uses a novel charge/discharge based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18 m 6-metal CMOS process. The platform was validated through a series of dry and wet measurements. Wet measurements in saline demonstrated the sensitivity of the platform in detecting moisture/ion ingress. Such a platform could be used both in accelerated soak studies and during the implant's life-time for monitoring the integrity of the chips packaging.

This paper presents the design of a low-power asynchronous pipelined time-to-digital converter (AP-TDC) to be employed in a time-domain signal processing system. The presented AP-TDC utilizes two novel concepts, namely time-domain subtraction and absolute value based algorithmic conversion. The design and simulation of the AP-TDC is done using a standard CMOS 65 nm process. The least-significant-bit resolution of the AP-TDC is designed to be 200 ps and the AP-TDC outputs 7-bit digital words with an ENOB of 6.2 bits. The dynamic range of the TDC is 25.4 ns and the TDC core consumes 38 μW from a supply voltage of 1V and has a total area of 1275 μm ² . When compared to a Flash TDC implementation using the same delay elements, power consumption, total area, and conversion time are reduced by 28.3%, 31.5%, and 24.6%, respectively. The AP-TDC has a figure-of-merit of 9.9-fJ/conversion step.

This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to operate in the subthreshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle information is used to find the minimum energy operation point, corresponding maximum clock frequency, as well as the dissipated energy per clock cycle. The application of the model is demonstrated by exploring the energy efficiency of pipelining, retiming, and register balancing. Simulation results, which are obtained during a fraction of SPICE simulation time, are validated by measurements on a wavelet-based cardiac event detector that was fabricated in 65-nm low-leakage high-threshold technology. The mean of the absolute modeling error is calculated as 5.2%, with a standard deviation of 6.6% over the measurement points. The cardiac event detector dissipates 0.88 pJ/sample at a supply voltage of 320 mV.

This paper presents the design of an ultra-low energy neural network that uses time-mode signal processing). Handwritten digit classification using a single-layer artificial neural network (ANN) with a Softmin-based activation function is described as an implementation example. To realize time-mode operation, the presented design makes use of monostable multivibrator-based multiplying analogue-to-time converters, fixed-width pulse generators and basic digital gates. The time-mode digit classification ANN was designed in a standard CMOS 0.18 μm IC process and operates from a supply voltage of 0.6 V. The system operates on the MNIST database of handwritten digits with quantized neuron weights and has a classification accuracy of 88%, which is typical for single-layer ANNs, while dissipating 65.74 pJ per classification with a speed of 2.37 k classifications per second. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.