Metallic glasses attract considerable interest due to their unique combination of superb properties and processability. Predicting their formation from known alloy parameters remains the major hindrance to the discovery of new systems. Here, we propose a descriptor based on the heuristics that structural and energetic ‘confusion’ obstructs crystalline growth, and demonstrate its validity by experiments on two well-known glass-forming alloy systems. We then develop a robust model for predicting glass formation ability based on the geometrical and energetic features of crystalline phases calculated ab initio in the AFLOW framework. Our findings indicate that the formation of metallic glass phases could be much more common than currently thought, with more than 17% of binary alloy systems potential glass formers. Our approach pinpoints favourable compositions and demonstrates that smart descriptors, based solely on alloy properties available in online repositories, offer the sought-after key for accelerated discovery of metallic glasses.

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.

The tunable solid-state thermal rectification of a three-terminal device is presented by asymmetric nonlinear far-field radiation. The experimental findings are supplemented with finite element analysis, with a maximum rectification ratio of 93.1%.