Spectral efficiency improvement is essential for mobile systems development in the light of growing demand for high data transmission rate. The Time-domain synchronous OFDM transmission system increases bandwidth utilization by time-domain channel estimation without any support from frequency-domain pilot signals. Channel identification methods use a training sequence, added at the beginning of every OFDM symbol. Sparse nature of the channel impulse response, which manifests itself during wireless broadband transmission, enables one to implement compressed sensing techniques for channel identification. Channel sparsity reduces the number of measurement samples required in channel reconstruction procedure, but they should be taken from the inter-block interference (IBI) free part of the received training sequence. If maximum delay spread of the channel is comparable with the length of the training sequence, the number of measurements within the IBI-free region may be insufficient for accurate channel identification. This paper discusses a new iterative approach to sparse channels estimation, which uses the measurements from outside the IBI-free region. The proposed solution is examined for simulated transmission over randomly generated doubly-selective channels when compared with the conventional CS technique and perfect channel state information condition. The experiments reveal an enhancement of the transmission quality in terms of SER for slow-time selective channels when both delays and gains of the channel impulse response are estimated with the orthogonal matching pursuit algorithm. Further improvement, also for transmission over moderate varying channels, is observed when the path delays are found in advance. A suitable frame structure is proposed to do so.

Greedy algorithms, like orthogonal matching pursuit (OMP), compressive sampling matching pursuit, and their modifications, are the popular methods of compressive sensing in sparse signal reconstruction. They are iterative in manner and often use a scaled value of the system noise energy as a reference threshold to decide when to stop the searching procedure. This letter presents an analytical analysis of the residual error and also of the difference of the successive residual errors in a general case of the greedy searching procedure, provided that the measurement error is an independent and identically distributed Gaussian stationary process. The obtained results show that the mean energy of the mentioned errors, just at the moment of perfect recovery of the signal support, depends only on the sparsity order and/or on the number of measurement samples. The results contributed to designing a practical stopping rule, which is a combination of those two errors. Numerical experiments with the new rule implemented in the OMP algorithm show that the number of executed iterations can be less spread around the true value of the signal sparsity in the mean sense. A quality of the sparse signal estimation is also preserved.

The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2^p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.

Many physical phenomena can be modeled by compressible signals, i.e., the signals with rapidly declining sample amplitudes. Although all the samples are usually nonzero, due to practical reasons such signals are attempted to be approximated as sparse ones. Because sparsity of compressible signals cannot be unambiguously determined, a decision about a particular sparse representation is often a result of comparison between a residual error energy of a reconstruction algorithm and some quality measure. The paper explores a relation between mean square error (MSE) of the recovered signal and the residual error. A novel, practical solution that controls the sparse approximation quality using a target MSE value is the result of these considerations. The solution was tested in numerical experiments using orthogonal matching pursuit (OMP) algorithm as the signal reconstruction procedure. The obtained results show that the proposed quality metric provides fine control over the approximation process of the compressible signals in the mean sense even though it has not been directly designed for use in compressed sensing methods such as OMP.

Hostile wireless environment requires use of sophisticated signal processing methods. The paper concerns on Ultra Wideband (UWB) transmission over Personal Area Networks (PAN) including MB-OFDM specification of physical layer. In presented work the transmission system with OFDM modulation was connected with LDPC encoder/decoder. Additionally the frame and bit error rate (FER and BER) of the system was decreased using results from the LDPC decoder in a kind of turbo equalization algorithm for better channel estimation. Computational block using evolutionary strategy, from genetic algorithms family, was also used in presented system. It was placed after SPA (Sum-Product Algorithm) decoder and is conditionally turned on in the decoding process. The result is increased effectiveness of the whole system, especially lower FER. The system was tested with two types of LDPC codes, depending on type of parity check matrices: randomly generated and constructed deterministically, optimized for practical decoder architecture implemented in the FPGA device.