This article proposes a reliable and secured polar coding for the network-oriented cloud control system (NOCCS) in the context of security, reliability, and scalability. A low-complexity variant of the 3-D chaos system is proposed to accomplish internal chaos-encryption-based polar coding for orthogonal frequency division multiplexing over an active power network (OFDM-AON) to ensure the reliability and security of the NOCCS. Internal encryption is achieved by disrupting the correlation of the information bits index and frozen bits index along with the subcarrier by the three chaotic behavioral sequences obtained by Chua's system while encoding polar code. The method is tested on the fiber optic channel between the cloud computing and a local controller placed at a significant distance, thoroughly connected through the fiber optic cable network, and utilizing a 16 quadrature amplitude modulation-OFDM (QAM-OFDM) signal transmission. Our experimental results and performance analysis demonstrate that the proposed encryption scheme produces a 2.5-dB gain in sensitivity on the local controller end at a bit error rate (BER) of 10 $^{-3}$ compared to the conventional QAM-OFDM. Furthermore, the spacing window for the key distribution is 10 $^{75}$ , which can be regarded as a protection degree against any brute-force attack from unauthorized optical network units that act as local controllers. Considering the BER enhancement, reliability, and security, the proposed QAM-OFDM-based chaos encryption polar encoding can be ranked as a suitable choice for the NOCCSs data transmission and protection against any brute-force or differential attacks.

Low-density parity-check (LDPC) codes are known to be one of the best error-correction coding (ECC) schemes in terms of correction performance. They have been utilized in many advanced data communication standards for which the codecs are typically implemented in custom integrated circuits (ICs). In this paper, we present a research work that shows that the LDPC coding scheme can also be applied in a system characterized by highly limited computational resources. We present a microcontroller-based application of an efficient LDPC encoding algorithm with efficient usage of memory resources for the code-parity-check matrix and the storage of the results of auxiliary computations. The developed implementation is intended for an IoT-type system, in which a low-complexity network node device encodes messages transmitted to a gateway. We present how the classic Richardson–Urbanke algorithm can be decomposed for the QC-LDPC subclass into cyclic shifts and GF(2) additions, directly corresponding to the CPU instructions. The experimental results show a significant gain in terms of memory usage and decoding timing of the proposed method in comparison with encoding with the direct parity check matrix representation. We also provide experimental comparisons with other known block codes (RS and BCH) showing that the memory requirements are not greater than for standard block codes, while the encoding time is reduced, which enables the energy consumption reduction. At the same time, the error-correction performance gain of LDPC codes is greater than for the mentioned standard block codes.

An approach to design protograph based low-density parity-check (LDPC) codes utilizing Mixed Integer Linear Programming (MILP) optimization is presented in this paper. The protograph (base graph) cyclic lifting for a class of quasi-cyclic (QC) LDPC codes is considered. In general, short cycles elimination is the primary optimization goal, possibly weighted by a metric of cycles connectivity. A notion of closed walks in the base graph is shown to be a convenient way for representing sources of cycles in the lifted graph. We express the condition for non-existence of a cycle in the lifted graph corresponding to a closed walk in the base graph in the form of a set of linear inequalities. Such inequalities, collected for all closed walks shorter than a desired limit corresponding to girth, form a set of linear constraints. Meanwhile, the longer closed walks can be reflected in a linear objective function of the optimization. The proposed combination of constraints and objective function forms an input to a MILP solver. As a result, a globally optimized code graph can be obtained. The method can be utilized for binary as well as nonbinary LDPC codes. Numerical results show that constructed codes can outperform similar codes deigned with reference heuristic search methods.

The concept of Low Density Parity Check (LDPC) coding over Galois Fields GF (q = 2^p) is a generalization of the industry standard binary LDPC coding. The performance for short block length codes is significantly higher for non-binary codes (over higher order GF fields), but on the other hand, the decoding complexity is increased. Therefore the hardware implementation of a decoder is still a challenging task. Most of the few implementations known from the literature use multiplierless computing units. In this article we present a different approach that does not exclude multiplier blocks from the decoder module. This approach is specifically intended for FPGA (Field Programmable Gate Array) implementation. We propose the decoding algorithm formulation that uses multiplications in the computation step of the Check Nodes and summations performed in the Bit Nodes. The main reason is to enable mapping a part of the algorithm to the multiplier cores available in the FPGA devices. In the article we present the decoder structure that has been developed and the construction of its building blocks. We also provide synthesis results for the Xilinx FPGAs and simulation results for a simple BPSK (Binary Phase Shift Keying) modulation model over AWGN (Additive White Gaussian Noise) channel.

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.