Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

Failure modes and mechanisms of AlGaN/GaN high-electron-mobility transistors are reviewed. Data from three de-accelerated tests are presented, which demonstrate a close correlation between failure modes and bias point. Maximum degradation was found in "semi-on" conditions, close to the maximum of hot-electron generation which was detected with the aid of electroluminescence (EL) measurements. This suggests a contribution of hot-electron effects to device degradation, at least at moderate drain bias (V_DS30-50 V), new failure mechanisms are triggered, which induce an increase of gate leakage current. The latter is possibly related with the inverse piezoelectric effect leading to defect generation due to strain relaxation, and/or to localized permanent breakdown of the AlGaN barrier layer. Results are compared with literature data throughout the text.

Physical mechanisms causing the efficiency droop in InGaN/GaN blue light-emitting diodes and remedies proposed for droop mitigation are classified and reviewed. Droop mechanisms taken into consideration are Auger recombination, reduced active volume effects, carrier delocalization, and carrier leakage. The latter can in turn be promoted by polarization charges, inefficient hole injection, asymmetry between electron and hole densities and transport properties, lateral current crowding, quantum-well overfly by ballistic electrons, defect-related tunneling, and saturation of radiative recombination. Reviewed droop remedies include increasing the thickness or number of the quantum wells, improving the lateral current uniformity, engineering the quantum barriers (including multi-layer and graded quantum barriers), using insertion or injection layers, engineering the electron-blocking layer (EBL) (including InAlN, graded, polarization-doped, and superlattice EBL), exploiting reversed polarization (by either inverted epitaxy or N-polar growth), and growing along semi- or non-polar orientations. Numerical device simulations of a reference device are used through the paper as a proof of concept for selected mechanisms and remedies.

Drain current dispersion effects are investigated in AlGaN-GaN HEMTs by means of pulsed, transient, and small-signal measurements. Gate- and drain-lag effects characterized by time constants in the order of 10/sup -5/-10/sup -4/ s cause dispersion between dc and pulsed output characteristics when the gate or the drain voltage are pulsed. An activation energy of 0.3 eV is extracted from temperature-dependent gate-lag measurements. We show that two-dimensional numerical device simulations accounting only for polarization charges and donor-like traps at the ungated AlGaN surface can quantitatively reproduce all dispersion effects observed experimentally in the different pulsing modes, provided that the measured activation energy is adopted as the energetic distance of surface traps from the valence-band edge. Within this hypothesis, simulations show that surface traps behave as hole traps during transients, interacting with holes attracted at the AlGaN surface by the negative polarization charge.

Long-term ON-state and OFF-state high-electric-field stress results are presented for unpassivated GaN/AlGaN/GaN high-electron-mobility transistors on SiC substrates. Because of the thin GaN cap layer, devices show minimal current-collapse effects prior to high-electric-field stress, despite the fact that they are not passivated. This comes at the price of a relatively high gate-leakage current. Under the assumption that donor-like electron traps are present within the GaN cap, two-dimensional numerical device simulations provide an explanation for the influence of the GaN cap layer on current collapse and for the correlation between the latter and the gate-leakage current. Both ON-state and OFF-state stresses produce simultaneous current-collapse increase and gate-leakage-current decrease, which can be interpreted to be the result of gate-drain surface degradation and reduced gate electron injection. This study shows that although the thin GaN cap layer is effective in suppressing surface-related dispersion effects in virgin devices, it does not, per se, protect the device from high-electric-field degradation, and it should, to this aim, be adopted in conjunction with other technological solutions like surface passivation, prepassivation surface treatments, and/or field-plate gate

High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.