A low temperature (T _max = 350 °C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si _0.5 Ge _0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 10 ¹⁶ cm ^-3 were fabricated. Ge pFETs are fabricated (T _max = 600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Epitaxial in situ doped Si_0.73Ge_0.27 alloys were grown selectively on patterned bulk Ge and bulk Si wafers. Si_0.73Ge_0.27 layers with a surface roughness of less than 3 nm were demonstrated. Selectively grown p⁺Si_0.73Ge_0.27 layers exhibited a resistivity of 3.5 mΩcm at a dopant concentration of 2.5 × 10¹⁹ boron atoms/cm³. P⁺/n diodes were fabricated by selectively growing p⁺- Si_0.73Ge_0.27 on n-doped bulk Ge and n-doped Si wafers, respectively. The geometrical leakage current contribution shifts from the perimeter to the bulk as the diode sizes increase. Extracted near midgap activation energies are similar to p⁺/n Ge junctions formed by ion implantation. This indicates that the reverse leakage current in p⁺/n Ge diodes fabricated with various doping methods, could originate from the same trap-assisted mechanism. Working p⁺/n diodes on Ge bulk substrates displayed a reverse current density as low as 2.2·10⁻² A/cm² which was found to be comparable to other literature data. The layers developed in this work can be used as an alternative method to form p⁺/n junctions on Ge substrates, showing comparable junction leakage results to ion implantation approaches.