G. Jayakumar

Dr. G. Jayakumar


Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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17 January 2019 in Nanotechnology
Verified
Journal Article
Open access
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GJG. Jayakumar
G. Jayakumar
MLMaxime Legallais
Maxime Legallais
PHPer-Erik Hellström
Per-Erik Hellström
MMMireille Mouis
Mireille Mouis
IPIsabelle Pignot-Paintrand
Isabelle Pignot-Paintrand
MÖMikael Östling
Mikael Östling
Silicon nanowire (SiNW) charge based biosensors are attractive for DNA sensing applications due to their compactness and large surface-to-volume ratio. Small feature size, low production cost, repeatability, high sensitivity and selectivity are some of the key requirements for biosensors. The most common e-beam manufacturing method employed to manufacture sub-nm SiNWs is both cost and time intensive. Therefore, we propose a highly reproducible CMOS industry grade low-cost process to fabricate SiNW based field effect transistors on 4"-wafers. The 60 nm wide SiNWs reported in this paper are fabricated using the sidewall transfer lithography process which is a self-aligned-double-patterning I-line lithography process that also facilitates encapsulation of the SiNW surface with a thin HfO2 layer on which DNA probes are grafted to finalize the biosensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bioprocesses. More specifically, based on a statistical analysis, we demonstrate that 85% of the tested devices exhibit a positive threshold voltage shift after DNA hybridization. These promising results make way for the monolithic integration of SiNW biosensors and CMOS circuitry to realize a point of care device which can offer reliable real time electrical readout.

2 February 2018 in IEEE Journal of the Electron Devices Society
Verified
Journal Article
Open access
AAAhmad Abedin
Ahmad Abedin
LZLaura Zurauskaite
Laura Zurauskaite
AAA. Asadollahi
A. Asadollahi
KGKonstantinos Garidis
Konstantinos Garidis
GJG. Jayakumar
G. Jayakumar
MOMikael Ostling
Mikael Ostling
A low temperature (T max = 350 °C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si 0.5 Ge 0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 10 16 cm -3 were fabricated. Ge pFETs are fabricated (T max = 600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

5 February 2024 in Applied Physics Letters
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Journal Article
Open access
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VKVaishnavi Kateel
Vaishnavi Kateel
MMMaxwel Gama Monteiro
Maxwel Gama Monteiro
SJSeyeob Jeong
Seyeob Jeong
GTGiacomo Talmelli
Giacomo Talmelli
GJG. Jayakumar
G. Jayakumar
SRSiddharth Rao
Siddharth Rao
Spin–orbit torque (SOT)-induced reversal of a ferromagnet in a magnetic tunnel junction (MTJ) is promising for next-generation novel magnetic memory and spin-logic devices. However, inherent limitations of single ferromagnetic-based free layer (FL) systems are low thermal stability and susceptibility to external magnetic stray fields. To overcome these challenges, synthetic antiferromagnets (SAFs) are integrated into MTJ devices to form hybrid free layers (HFLs); this FL system enables tunability of thermal stability and stray field experienced by the FL, simultaneously lowering the SOT-induced switching currents. Here, we investigate the impact of net magnetization of the SAF-based HFL on the field and current-driven switching behavior. We observe that nearly compensated SAF-HFL systems demonstrate a higher proportion of switching failures at the device level than the uncompensated SAF-HFL systems in both current and field-driven schemes. Micro-magnetic simulations and thin film characterization of SAF-HFL show that the device-level stochasticity arises due to a dynamic decoupling within the nearly compensated SAF systems. We show that optimizing the SAF-HFL systems to have uncompensated magnetization mitigates this stochasticity and improves the SOT switching current for Pt-based SOT channel by at least 20% across the entire tested pulse width range down to 300 ps, thus leading to reliable switching of SOT-MTJs with SAF-HFL stacks.

18 March 2019 in Nanotechnology
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Journal Article
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GJG. Jayakumar
G. Jayakumar
MÖM Östling
M Östling
Silicon nanowires (SiNWs) are a widely used technology for sensing applications. Complementary metal-oxide-semiconductor (CMOS) integration of SiNWs advances lab-on-chip (LOC) technology and offers opportunities for read-out circuit integration, selective and multiplexed detection. In this work, we propose novel scalable pixel-based biosensors exploiting the integration of SiNWs with CMOS in fully-depleted silicon-on-insulator technology. A detailed description of the wafer-scale fabrication of SiNW pixels using the CMOS compatible sidewall-transfer-lithography as an alternative to widely investigated time inefficient e-beam lithography is presented. Each 60 nm wide SiNWs sensor is monolithically connected to a control transistor and novel on-chip fluid-gate forming an individual pixel that can be operated in two modes: biasing transistor frontgate (V G) or substrate backgate (V BG). We also present the first electrical results of single N and P-type SiNW pixels. In frontgate mode, N and P-type SiNW pixels exhibit subthreshold slope (SS) ≈ 70-80 mV/dec and I on/I off ≈ 105. The N-type and P-type pixels have an average threshold voltage, Vth of -1.7 V and 0.85 V respectively. In the backgate mode, N and P-type SiNW pixels exhibit SS ≈ 100-150 mV/dec and I on/I off ≈ 106. The N and P-type pixels have an average V th of 5 V and -2.5 V respectively. Further, the influence of the backgate and frontgate voltage on the switching characteristics of the SiNW pixels is also studied. In the frontgate mode, the V th of the SiNW pixels can be tuned at 0.2 V for 1 V change in V BG for N-type or at -0.2 V for -1 V change in V BG for P-type pixels. In the backgate mode, it is found that for stable operation of the pixels, the V G of the N and P-type transistors must be in the range 0.5-2.5 V and 0 V to -2.5 V respectively.

25 October 2018 in Micromachines
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GJG. Jayakumar
G. Jayakumar
PHPer-Erik Hellström
Per-Erik Hellström
MÖMikael Östling
Mikael Östling
Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (VG) and backgate voltage (VBG). The liquid potential can be monitored using the FG. We report the transfer characteristics (ID-VG) of N- and P-type SiRi pixels. Further, the ID-VG characteristics of the SiRis are studied at different VBG. The application of VBG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (VTH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large VBG (≥25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large VBG to switch ON. Thus, P-type pixels exhibit excellent ION/IOFF ≥ 106, SS of 70–80 mV/dec and VTH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

1 May 2019 in Microelectronic Engineering
Verified
Journal Article
Closed access
GJG. Jayakumar
G. Jayakumar
PHP.-E. Hellström
P.-E. Hellström
MÖM. Östling
M. Östling