Monolithic integration of complementary field-effect transistor (CFET) with two-dimensional (2D) materials channels has been challenging due to the deteriorated performance of p-type transistors, especially using top-gate dielectric. In this work, we demonstrate monolithic 3D stacking CFET based on chemical-vapor-deposition (CVD) grown 2D materials channels for low-power integrated circuits (ICs). The top gate p-channel bilayer WSe 2 transistor is optimized by low-temperature post-metal annealing, achieving a record-high $\text{I}_{\text{o}\text{n}}$ of -594$\mu$A/$\mu$m and $\text{G}_{\text{m}}$ of -244$\mu$S/$\mu$m at $\text{V}_{\text{d}}=-2$V with a short $\text{L}_{\text{c}\text{h}}=135$ nm, far exceeding previous results. Furthermore, full-output-swing inverters with rail-to-rail operations and below-nanowatt low power are achieved owing to the symmetrical threshold voltages for WSe 2 pFETs and MoS 2 nFETs. The 4T SRAM and 16T half-adder circuit units based on CFET design are also experimentally demonstrated for the first time, presenting the superiority of CFET in performance, power, and area (PPA).

4D printing is utilized to fabricate of thermo-deformable bow-tie antenna to fulfill some special applications with limited space or changing antenna property. In this paper, 4D printing is used to manufacture nylon and carbon fiber laminated composite material. The bow-tie antenna is installed on the surface of the composite material, and the carbon fiber is energized and heated, which causes thermal deformation of the substrate to reconfigure the antenna feature. The deformation mechanism of the composite material is explained, the characteristics of the thermally deformed bow-tie antenna with power applied to carbon fiber are analyzed. The results show that the energized carbon fiber heats up, causing the structure to stretch to a flat, with a maximum gain of 2.37 dBi and the −10 dB bandwidth being 4.28–4.64 GHz and 5.16–5.52 GHz, and the half-power beamwidth is greater than 60°. The structure bends at a 30° angle with a maximum gain of 3.58 dBi in the absence of external power, delivering a −10 dB bandwidth range of 4.12–5.6 GHz and a half-power beamwidth close to 45°. The customization of antenna radiation patterns and antenna gain can be readily tuned with power control.

Al₂O₃/GeO_x/Ge gate stack fabricated by an in situ cycling ozone oxidation (COO) method in the atomic layer deposition (ALD) system at low temperature is systematically investigated. Excellent electrical characteristics such as minimum interface trap density as low as 1.9 × 10¹¹cm⁻²eV⁻¹ have been obtained by COO treatment. The impact of COO treatment against the band alignment of Al₂O₃ with respect to Ge is studied by x-ray photoelectron spectroscopy (XPS) and spectroscopic ellipsometry (SE). Based on both XPS and SE studies, the origin of gate leakage in the ALD-Al₂O₃ is attributed to the sub-gap states, which may be correlated to the OH-related groups in Al₂O₃ network. It is demonstrated that the COO method is effective in repairing the OH-related defects in high-k dielectrics as well as forming superior high-k/Ge interface for high performance Ge MOS devices.

By focusing on the Al/Al₂O₃/InP capacitor structure, impacts on interface modification using sulfur and nitrogen passivations against traps and charge formation are systematically investigated. Improved electrical characteristics with low leakage current density, hysteresis, interface trap density, and capacitance frequency dispersion are demonstrated after sulfur or nitride interface passivations. It is clarified that sulfur interface passivation is more effective in reducing the interface traps, while nitride interface passivation shows stronger impact on suppressing the generation of bulk and border traps and the negative interface charges. A possible model based on network modification is proposed to explain the mechanism of the different trap and charge behaviors for sulfur and nitride interface passivation.

The interface of the two-dimensional material plays a crucial role in the properties of the material itself. When 2D materials are used as channel for electrical devices, negative influence from surface contaminations during fabrication process should be avoided to ensure the device performance and the reliability. In this article, the impacts as well as its mechanisms of interface contaminations on MoS2 field effect transistors were studied. An effective method using an atomic layer deposition (ALD) grown Al2O3 dielectric layer to reduce exposure time of MoS2 during processing was introduced. Combine with annealing process, the fabricated MoS2 FETs with a Al2O3 protective layer demonstrate a high On/Off current ratio of 5Χ107, and a hysteresis of 80 mV in terms of decent reliability. Sulfur repair mechanism on MoS2/Al2O3 interface during annealing is revealed to explained the enhancement of devices performance. This method can also be adopted in other 2D materials, paving a path for the next generation flexible electronics application.