Multiple-output DC–DC converters are essential in a multitude of applications where different DC output voltages are required. The interest and importance of this type of multiport configuration is also reflected in that many electronics manufacturers currently develop integrated solutions. Traditionally, the different output voltages required are obtained by means of a transformer with several windings, which are in addition to providing electrical isolation. However, the current trend in the development of multiple-output DC–DC converters follows general aspects, such as low losses, high-power density, and high efficiency, as well as the development of new architectures and control strategies. Certainly, simple structures with a reduced number of components and power switches will be one of the new trends, especially to reduce the size. In this sense, the incorporation of devices with a Wide Band Gap (WBG), particularly Gallium Nitride (GaN) and Silicon Carbide (SiC), will establish future trends, advantages, and disadvantages in the development and applications of multiple-output DC–DC converters. In this paper, we present a review of the most important topics related to multiple-output DC–DC converters based on their main topologies and configurations, applications, solutions, and trends. A wide variety of configurations and topologies of multiple-output DC–DC converters are shown (more than 30), isolated and non-isolated, single and multiple switches, and based on soft and hard switching techniques, which are used in many different applications and solutions.

In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in field-programmable gate array (FPGA)-based designs, using standard resources available in those devices and with minimal impact on the standard FPGA design flow. Given the limited amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging effects. Experimental results, obtained in circuits of increasing complexity (where several sensors need to be used), are presented and discussed, demonstrating the good performance of the proposed sensor, as well as its low cost in terms of area overhead and power consumption. Results of aging experiments based on the standard US MIL-STD-883 Method 1015.50 “Burn-In Test” are also reported, demonstrating that the effect of aging on the sensor is negligible compared to that on the circuit under test, which is a key point for practical applicability. The proposed approach provides a novel and efficient solution to the specific FPGA design problems in this context, which are different from those addressed in application-specific integrated circuit design.

This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensor's performance degradation works in favor of the predictive error detection. The sensor is out of the signal path. Performance error prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation. Such errors must not occur in safety-critical systems (automotive, health, space). A sensor insertion algorithm is also proposed, to selectively insert them in key locations in the design. Sensors can be always active or at pre-defined states. Simulation results are presented for a balanced pipeline multiplier in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM). It is shown that the impact of aging degradation and/or PVT (Process, power supply Voltage and Temperature) variations on the sensor enhance error prediction.

Bipolar DC grids have become an adequate solution for high-power microgrids. This is mainly due to the fact that this configuration has a greater power transmission capacity. In bipolar DC grids, any distributed generation system can be connected through DC-DC converters, which must have a monopolar input and a bipolar output. In this paper, a DC-DC converter based on the combination of single-ended primary-inductor converter (SEPIC) and Ćuk converters is proposed, to connect a photovoltaic (PV) system to a bipolar DC grid. This topology has, as main advantages, a reduced number of components and a high efficiency. Furthermore, it can contribute to regulate/balance voltage in bipolar DC grids. To control the proposed converter, any of the techniques described in the literature and applied to converters of a single input and single output can be used. An experimental prototype of a DC-DC converter with bipolar output based on the combination of SEPIC and Ćuk converters was developed. On the other hand, a perturb and observe method (P and O) has been applied to control the converter and has allowed maximum power point tracking (MPPT). The combined converter was connected in island mode and in parallel with a bipolar DC microgrid. The obtained results have allowed to verify the behavior of the combined converter with the applied strategy.

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on user's requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

Electronic design of high-performance digital systems in nano-scale CMOS technologies under Process, power supply Voltage, Temperature and Aging (PVTA) variations is a challenging process. Such variations induce abnormal timing delays leading to systems errors, harmful in safety-critical applications. Performance Failure Prediction (PFP), instead of error detection, becomes necessary, particularly in the presence of aging effects. In this paper, an on-line BIST methodology for PFP in a standard cell design flow is proposed. The methodology is based on abnormal delay detection associated with critical signal paths. PVTA-aware aging sensors are designed. Multilevel simulation is used. Functional and structural test pattern generation is performed, targeting the detection of critical path delay faults. A sensor insertion technique is proposed, together with an up-graded version of a proprietary software tool, DyDA. Finally, a novel strategy for gate-level Aging fault injection is proposed, using the concept of an Aging de-rating factor. Results are presented for a Serial Parallel Interface (SPI) controller, designed with commercial UMC 130nm CMOS technology and Faraday™ cell library. Only seven sensors are required to monitor unsafe performance operation, due to Negative Bias Thermal Instability (NBTI)-induced aging.