A through-silicon via (TSV) is a conducting copper nail, which provides an electrical connection through a substrate, and is expected to be used extensively to provide high-speed interconnects between the top and bottom of an active die. However, some TSV structural defects such as pinholes and voids are difficult to capture as they commonly affect TSV performance parameters rather than TSV logical function. In order to electrically detect failures, it is necessary to study and analyze electrical characteristics of defects in advance. Testing TSV interconnects for manufacturing defects poses major challenges, and new design-for-test techniques are needed. Here, a novel nondestructive defect detection method using machine learning (ML) is proposed in order to detect void, short, and open defects in TSV-based 3-D ICs. A supervised ML approach is used to build a classification model from training S-parameter data sets containing the defected TSV and the normal TSV. The performance of the random forest classifier is tested for various amounts of void, short, and open defects in TSV-based 3-D-stacked ICs with satisfactory results.

The AES IP with different architectures implemented using ASIC and FPGA are presented in this paper. For ASIC design, the performance of the AES IP has been evaluated by comparing its area/power/delay, synthesized with TSMC 0.35 mum cell library and TSMC 0.18 mum cell library. The performance estimation in FPGA implementation with Altera and Xilinx platforms are also presented. The hardware implementation results of the proposed architecture with Mixcolumn/preprocess InvMixcolumn to perform Mixcolumn/InvMixcolumn transformation has less area cost as compared with previous relevant architecture. Due to the I/O bottlenecks between host processor and a stand alone AES module, a reconfigurable bandwidth sharing architecture is proposed to enhance the system performance

Medication safety administration is a complicated process involving the information of patients, drugs, and data storage. The sensitive data transmitted through wireless sensor networks (WSNs) from Internet of things (IoT) over an insecure channel is vulnerable to several threats and needs proper attention to be secured from adversaries. Taking medication safety into consideration, this paper presents a secure authentication protocol for wireless medical sensor networks. The XOR scheme-based algorithm is applied to achieve the purposes of data confidentiality. The proposed architecture is realized as hardware in a field-programmable gate array (FPGA) device which acts as a secure edge computing device. The performance of the proposed protocol is evaluated and simulated via Verilog hardware description language. The functionality of the proposed protocol is verified using the Altera Quartus II software tool and implemented in the Altera Cyclone II DE2-70 FPGA development module. Furthermore, the output signals from the FPGA are measured in the 16702A logic analyzer system to demonstrate real-time functional verification.

Stacked die package using capacitive-based chip-to-chip signaling offers low energy-per-bit costs and high I/O density. Many previously published works on capacitive proximity I/O have focused on mechanical methods for accurate chip alignment. This paper explores design considerations to address stacked die structures with differential signaling chip-to-chip communication based on capacitive coupling. The signal and noise properties of capacitively coupled channels are studied using a 3-D electromagnetic field solver to extract mixed-mode scattering parameters of the differential signal pads. We present side differential and corner differential arrangements and compare their ability to reject noise. We then formulate a functional data analysis approach for assessing the signal transmission quality. Our results indicate that the differential transmitter and receiver pads arrangement and placement can significantly affect the interaction between a channel and its nearest neighbors. The preferred choice for I/O pad placement design depends on the placement arrangements and the overlap ratio of the differential I/O pads.