A through-silicon via (TSV) is a conducting copper nail, which provides an electrical connection through a substrate, and is expected to be used extensively to provide high-speed interconnects between the top and bottom of an active die. However, some TSV structural defects such as pinholes and voids are difficult to capture as they commonly affect TSV performance parameters rather than TSV logical function. In order to electrically detect failures, it is necessary to study and analyze electrical characteristics of defects in advance. Testing TSV interconnects for manufacturing defects poses major challenges, and new design-for-test techniques are needed. Here, a novel nondestructive defect detection method using machine learning (ML) is proposed in order to detect void, short, and open defects in TSV-based 3-D ICs. A supervised ML approach is used to build a classification model from training S-parameter data sets containing the defected TSV and the normal TSV. The performance of the random forest classifier is tested for various amounts of void, short, and open defects in TSV-based 3-D-stacked ICs with satisfactory results.

Thanks to advanced technologies, ultra-high-frequency limit order book (LOB) data are now available to data analysts. An LOB contains comprehensive information on all transactions in a market. We use LOB data to investigate the high-frequency dynamics of market supply and demand (S–D) and inspect their impacts on intra-daily market trends. The intra-daily S–D curves are fitted with B-spline basis functions. Technique of multi-resolution is introduced to capture inhomogeneous curvature of the S–D curves and a lasso-type criterion is employed to select a common basis set. Based on empirical evidence, we model the time varying coefficients in the B-spline interpolation by vector autoregressive models of order $p(\ge 1)$. The Xgboost algorithm is employed to extract information from the areas under the S–D curves to predict the intra-daily market trends. In the empirical study, we analyze the LOB data from LOBSTER (https://lobsterdata.com/). The results show that the proposed approach is able to recover the S–D curves and has satisfactory performance on both curve and market trend predictions.

Stacked die package using capacitive-based chip-to-chip signaling offers low energy-per-bit costs and high I/O density. Many previously published works on capacitive proximity I/O have focused on mechanical methods for accurate chip alignment. This paper explores design considerations to address stacked die structures with differential signaling chip-to-chip communication based on capacitive coupling. The signal and noise properties of capacitively coupled channels are studied using a 3-D electromagnetic field solver to extract mixed-mode scattering parameters of the differential signal pads. We present side differential and corner differential arrangements and compare their ability to reject noise. We then formulate a functional data analysis approach for assessing the signal transmission quality. Our results indicate that the differential transmitter and receiver pads arrangement and placement can significantly affect the interaction between a channel and its nearest neighbors. The preferred choice for I/O pad placement design depends on the placement arrangements and the overlap ratio of the differential I/O pads.