This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in the range of 0.3–0.5 V. In particular, a dc voltage gain of 25.16 dB, a gain-bandwidth product of 131.9 kHz with a capacitive load of 10 pF, and a static current consumption of only 557 nA are estimated at V_DD = 0.5 V. Moreover, the circuit behavior with respect to process and temperature variations was verified. Finally, the proposed amplifier is employed in a switched-capacitor integrator and in a sample-and-hold circuit to prove its functionality in case-study applications.

In this work, we introduce an ultra-low voltage, ultra-low power, inverter-based, discrete-time, 1st order Σ modulator. It exploits an original switched-capacitor integrator to achieve interesting performances with supply voltages as low as 0.25 V. It also employs a clock-boosting technique to improve pass-gate operation. A prototype has been designed and produced using a 0.18 μm CMOS process by UMC. The modulator reaches an SNDR of 37.2 dB at a voltage of 0.25 V, with a power consumption of only 2.1 nW, corresponding to a FOM of 140.3 dB. The DC characteristics show an offset of 4.3 mV, a gain error of 2.5% (standard deviations), with an INL of 0.6%.

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage $\mathsf{\Delta }\mathsf{\Sigma }$ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based $\mathsf{\Delta }\mathsf{\Sigma }$ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence^TM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

If not properly initiated, even-stage ring oscillators may resonate in undesirable ways. When this occurs, their output frequency can be higher than expected and they can no longer be employed as VCOs in PLL designs. In this paper, we analyze this issue and then we propose a novel startup circuit that can be used in differential, even-stage ring oscillators. This design is produced using a 0.30 µm CMOS process. Measurements performed on test chips show that our circuit always prevents spurious oscillation modes from arising. On the contrary, if the proper startup is disabled, unwanted modes may occur, especially at low temperatures or with little bias current. Moreover, consisting of just two MOSFETs per oscillator stage, the proposed circuit is also very simple and efficient in terms of area and power dissipation.