This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in the range of 0.3–0.5 V. In particular, a dc voltage gain of 25.16 dB, a gain-bandwidth product of 131.9 kHz with a capacitive load of 10 pF, and a static current consumption of only 557 nA are estimated at V_DD = 0.5 V. Moreover, the circuit behavior with respect to process and temperature variations was verified. Finally, the proposed amplifier is employed in a switched-capacitor integrator and in a sample-and-hold circuit to prove its functionality in case-study applications.

A compact electronic circuit capable of performing Electrochemical Impedance Spectroscopy (EIS) on either single Lithium-ion cells or modules formed by the series of two cells is presented. The proposed device, named Double Cell Management Unit (DCMU), constitutes an important improvement to a recently proposed cell management unit, which combined EIS acquisition functions with a multichannel sensor interface compatible with thermistors, strain-gauges and moisture detectors. The proposed circuit maintains the versatility of the previous version and significantly extends the EIS frequency range, allowing vector impedance measurements from 0.1 Hz to about 15 kHz. The capability of handling both single Lithium-ion cells or series of two cells is obtained by adding a few external components to the previous version. This also allowed increasing the stimulation current to a maximum amplitude of 200 mA, resulting in improved resolution. Experiments consisting in EIS acquisition performed on batteries of different capacity at different temperatures and states of charge are described. Estimated impedance resolution (standard deviation) is 20 μΩ obtained at 1 kHz with a stimulation current of 100 mA amplitude.

To better asses the ageing and to reduce the hazards involved in the use of Lithium-Ion Batteries, multi-measurand monitoring units and strategies are urged. In this paper, a Cell Management Unit, based on the SENSIPLUS chip, a recently introduced multichannel, multi-mode sensor interface, is described. SENSIPLUS is a single System on a Chip combined with a reduced number of external components, resulting in a highly miniaturized device, built on 20 × 8 mm² printed circuit board. Thanks to SENSIPLUS’ versatility, the proposed system is capable of performing direct measurements (EIS, cell voltage) on the cell it is applied to, and reading different kinds of sensors. The SENSIPLUS versatile digital communication interface, combined with a digital isolator, enable connection of several devices to a single bus for parallel monitoring a large number of cells connected in series. Experiments performed by connecting the proposed system to a commercial Lithium-Ion Battery and to capacitive and resistive sensors are described. In particular, the capability of measuring the cell internal impedance with a resolution of 120 μΩ is demonstrated.

The design of low-phase-noise fully integrated frequency references is often a critical aspect in the development of low-cost integrated circuits for communication interfaces, sensing platforms, and biomedical applications. This work first discusses relaxation oscillator topologies and design approaches aimed at minimizing the phase noise; then, a single-comparator low-phase-noise RC relaxation oscillator is proposed, featuring a novel comparator self-threshold-adjustment technique. The oscillator was designed for a 10 MHz oscillation frequency. Electrical simulations performed on a 0.18 μm CMOS design confirmed that the proposed technique effectively rejects the flicker component of the comparator noise, allowing for a 152 dBc/Hz figure of merit at a 1 kHz offset frequency. The standard deviation of the jitter accumulated across 10k oscillation cycles is lower than 4 ns. The simulated current consumption of the circuit is equal to 50.8 μA with a 1.8 V supply voltage. The temperature sensitivity of the oscillation frequency is also notably low, as its worst-case value across process corners is equal to −20.8 ppm/°C from −55 °C to 125 °C.

In this work, we introduce an ultra-low voltage, ultra-low power, inverter-based, discrete-time, 1st order Σ modulator. It exploits an original switched-capacitor integrator to achieve interesting performances with supply voltages as low as 0.25 V. It also employs a clock-boosting technique to improve pass-gate operation. A prototype has been designed and produced using a 0.18 μm CMOS process by UMC. The modulator reaches an SNDR of 37.2 dB at a voltage of 0.25 V, with a power consumption of only 2.1 nW, corresponding to a FOM of 140.3 dB. The DC characteristics show an offset of 4.3 mV, a gain error of 2.5% (standard deviations), with an INL of 0.6%.

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage $\mathsf{\Delta }\mathsf{\Sigma }$ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based $\mathsf{\Delta }\mathsf{\Sigma }$ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the Cadence^TM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.