This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology.

Irradiation tests on 90 nm CMOS devices at different total ionizing doses lead to new insights into degradation mechanisms in gate oxides and lateral isolation structures and into their impact on gate and drain current noise sources. The action of lateral parasitic transistors and their physical parameters are studied in different operating conditions. The main focus is on 1/f noise, which is one of the few parameters which are sizably affected by irradiation. Irradiation effects on the noise in the gate current are discussed in this paper for the first time. The analysis of the behavior of thick oxide I/O transistors provides a comparison both with thin oxide core devices and with previous, less scaled CMOS generations.

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO₂) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO₂ )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.