Advances in manufacturing technologies and the recent explosion of materials and methods for creating additively manufactured devices has opened new avenues for novel heat sink designs that can be optimized for flow and conduction considerations. This review paper highlights many of the recent successes and challenges associated with the utilization of “3 D printed” heat sinks for applications in electronics cooling. The purpose is to evaluate the current state of the art in additively manufactured thermal management solutions and the underlying physics and engineering approaches that illustrate the great promise of this emerging sector. The emphasis is therefore not only on the underlying strengths of additive manufacturing, such as its ability to greatly expand the realm of spatial and surface design for heat transfer, but also to illustrate some of its drawbacks that hinder its utilities in certain applications, such as the dearth of materials it can handle. This work looks toward future possibilities of custom designed heat removal schemes which utilize nontraditional geometries that were previously impossible using conventional machining methods.

Miniaturization as well as manufacturing processes that electronics devices are subjected to often results in to increase in operational parameters such as current density, temperature, mechanical load, and with potential to induce stresses that may be detrimental to device reliability. Past studies have identified some failure mechanisms common to these devices. Examples of these failure mechanisms include fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation, and time-dependent dielectric breakdown. While some review activities related to reliability model development based on these failure mechanisms can be easily found in literature, to the best of our knowledge, a single review paper, which captures the reliability model progresses made over the past four decades across these failure mechanisms in comparison with Standards such as Joint Electron Device Engineering Council (JEDEC) and Institute for Printed Circuits (IPC) is to the best of our knowledge lacking. To fill this gap, a detailed review of failure mechanism driven reliability models, with emphasis on physics of failure (PoF) for power electronics was carried out in this paper. Although, other failure mechanisms exist, our review is only limited to fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation, and time-dependent dielectric breakdown. It was found that most reliability research modeling efforts are yet to be fully integrated into Standards.

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are excellent power semiconductor devices due to their superior material properties compared to their silicon (Si) counterparts. It has demonstrated a fast switching speed with high dV/dt, enabling the designer to push the switching frequency toward the MHz range. However, traditional wire-bonded packaging becomes a limiting factor in fully harnessing the benefits offered by these advanced power devices, as it is likely to introduce voltage overshoot, oscillation, parasitic turn-on, and electromagnetic interference (EMI) issues; thus, improved and advanced packaging structures are a must to bridge the gap. Besides, the unique electrical behavior and footprint of GaN compared to Si and Si carbide make them have different requirements for power module integration. To seek a viable solution, a globally optimized double-sided cooled, gate driver integrated 650-V/60-A GaN half-bridge power module is presented herein. The proposed 3-D integrated hybrid solution delivers an optimized package, having power loop inductance and thermal resistance as low as 0.91 nH and $0.38~^{\circ }\text{C}$ /W, respectively, which is verified using simulation and experimental results. The overall utility of the design improved proportionately by introducing simple, yet effective electrical/thermal codesign approaches, which can be applied to future power modules, designed for separate applications.

As high voltage, wide-band-gap power modules increase in power density with high switching frequency, they create localized hot spots and harmful electromagnetic interference (EMI). If not treated properly, these issues can drastically reduce the reliability of the devices. In this article, we propose a solution to address both of these challenges created by power module building blocks which are designed for use in a hybrid-electric aircraft traction inverter. Additive manufacturing is used to fabricate a nonmetallic jet impingement device to decrease power module temperatures. Moreover, the nonmetallic structure limits the accentuation of EMI created by the module operating at high switching frequencies. Conjugate heat transfer simulations are used to predict the thermal performance of the cooler. In this article, a reduction of maximum die temperatures is observed, along with an increase in temperature uniformity throughout the base plate. Experimental results show a minimum thermal resistance of 0.1 K/W and an average heat transfer coefficient up to 3600 W/m ² .K at peak operation. Finally, EMI tests are performed to show a two orders of magnitude reduction of parasitic capacitance using the nonmetallic cooler compared with a metallic heat sink. This directly leads to a 25 dB decrease in the common mode noise.

This article proposes an insulation design strategy of laminated busbar to avoid partial discharge (PD) in more-electric aircraft (MEA) applications. During high-altitude operation, the converters for MEA are exposed to low air pressure, making partial discharge being triggered easier. But blindly increasing the insulation results in excessive parasitic inductance and degraded switching performance, which lead to serve losses and electromagnetic interference (EMI) problems during high-frequency switching operations. This article targets this issue and conducts a systematic study for laminated busbars in these high-density converters for MEA application. Moreover, it proposes a model-based codesign strategy to simultaneously optimize the busbar's stray inductance control and insulation layer design. To verify the design strategy, a busbar for a three-level (3L) 450-kVA converter is designed, fabricated, and evaluated. The measured minimum partial-discharge inception voltage is 43% higher than the rated voltage at 0.2 atm. Moreover, busbar stray inductance of 12.0 nH is achieved, which is lower than published literature for 3L converters. The low-inductance busbar can fully exploit the advantage of SiC- mosfet , helping it reduce switching loss by 66.7% at 1 kV 350 A with minimum voltage overshoots.