This paper proposes novel solutions for the application of air pollution monitoring systems in so called ‘smart cities’. A possibility of the implementation of a relatively dense network of wireless air pollution sensors that can collect and process data in real time was the motive behind our research and investigations. We discuss the concept of the wireless sensor network, taking into account the structure of the urban development in cities and we present a novel signal processing algorithm that may be used to control the communication scheme between particular sensors and an external network. We placed a special emphasis on the computational complexity to facilitate the implementation directly at the transistor level of particular sensors. The algorithm was verified using real data obtained from air pollution sensors installed in Krakow, Poland. To ensure sufficient robustness of the variability of input data, we artificially added high amplitude noise to the real data we obtained. This paper demonstrates the performance of the algorithm. This algorithm allows for the reduction of the noise amplitude by 23 dB and enables a reduction of the number of wireless communication sessions with a base station (BS) by 70%–80%. We also present selected measurement results of a prototype current-mode digital-to-analogue converter to be used in the sensors, for signal resolutions up to 7 bits.

Complexity of clock generator is one of the most important parameters in the design and optimization of switched-capacitor (SC) finite impulse response (FIR) filters. There are different SC FIR filter architectures. Some of them need a simple clock generator but the others require a quite complicated multiphase clock system. In the latter case an external clock system (i.e., outside the integrated circuit) is unrealistic because of a great number of the required external pins. We have implemented various SC FIR filter architectures together with complex internal clock generators in the CMOS 0.8 μm and 0.35 μm technologies. One of the most important problems in the design process was the optimization of waveforms and widths of the clock impulses. SC FIR filters are very sensitive to parameters of clock systems. Thus the clock generators must be designed very precisely. We demonstrate results of the design of the 64-phase clock generator for a programmable rotator SC FIR filter. In our approach the width of the clock impulses is controlled by two external signals. This is a very convenient solution, because optimization of the clock impulses, which was difficult in other approaches, is currently much easier. The internal clock generator area is ca. 0.15 mm² in the CMOS 0.35 μm technology, i.e., only 7 % of the entire SC FIR filter chip area.

Multiplexers are one of the most important elements in readout front-end ASICs for multi-element detectors in medical imaging. In the paper a fully asynchronous multiplexer with limited hierarchical de-randomization mechanism has been presented. The hierarchical mechanism prevents collisions in the system, which occur when two or more channels attempts to connect to the output stage. The proposed mechanism enables sequential reading out each of them eliminating that potential collision problem. The results presented in this paper are shown for the case of eight input channels, however the proposed technique can be easily extended to an arbitrary large number of channels. The circuit consumes 15μW at the power supply of 0.7V, enabling data processing (detection + readout) with 20 MHz frequency resulting in 1pJ energy used to detect one channel. While in a stand-by mode the circuit dissipates 2nW.