This paper presents a complementary metal-oxide-semiconductor (CMOS) implementation of a conscience mechanism used to improve the effectiveness of learning in the winner-takes-all (WTA) artificial neural networks (ANNs) realized at the transistor level. This mechanism makes it possible to eliminate the effect of the so-called ¿dead neurons,¿ which do not take part in the learning phase competition. These neurons usually have a detrimental effect on the network performance, increasing the quantization error. The proposed mechanism comes as part of the analog implementation of the WTA neural networks (NNs) designed for applications to ultralow power portable diagnostic devices for online analysis of ECG biomedical signals. The study presents Matlab simulations of the network's model, discusses postlayout circuit level simulations and includes results of measurement completed for the physical realization of the circuit.

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18-μm technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 μm ² . When operating in the L2 mode, the circuit dissipates 85 μW of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 μW from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

Neural networks (NNs) implemented at the transistor level are powerful adaptive systems. They can perform hundreds of operations in parallel but at the expense of a large number of building blocks. In the case of analog realization, an extremely low chip area and low power dissipation can be achieved. To accomplish this, the building blocks should be simple. This brief presents a new current-mode low-complexity flexible adaptive mechanism (ADM) with a strongly reduced leakage in analog memory. Input signals ranging from 0.5 to 20 μA are held for 10-50 ms, with the leakage rate from 0.2%/ms to 0.04%/ms, respectively, depending on temperature. A small storage capacitor of 200 fF enables a short write time ( <; 100 ns). A single ADM cell occupies 1400 μm² when realized in the Taiwan Semiconductor Manufacturing Company Ltd. CMOS 0.18-μm technology. The potential application of this NN is envisioned in a mobile platform based on a wireless sensor network to be used for online analysis of electrocardiography signals.

In this work, we propose a novel metaheuristic algorithm that evolved from a conventional particle swarm optimization (PSO) algorithm for application in miniaturized devices and systems that require low energy consumption. The modifications allowed us to substantially reduce the computational complexity of the PSO algorithm, translating to reduced energy consumption in hardware implementation. This is a paramount feature in the devices used, for example, in wireless sensor networks (WSNs) or wireless body area sensors (WBANs), in which particular devices have limited access to a power source. Various swarm algorithms are widely used in solving problems that require searching for an optimal solution, with simultaneous occurrence of a different number of sub-optimal solutions. This makes the hardware implementation worthy of consideration. However, hardware implementation of the conventional PSO algorithm is challenging task. One of the issues is an efficient implementation of the randomization function. In this work, we propose novel methods to work around this problem. In the proposed approach, we replaced the block responsible for generating random values using deterministic methods, which differentiate the trajectories of particular particles in the swarm. Comprehensive investigations in the software model of the modified algorithm have shown that its performance is comparable with or even surpasses the conventional PSO algorithm in a multitude of scenarios. The proposed algorithm was tested with numerous fitness functions to verify its flexibility and adaptiveness to different problems. The paper also presents the hardware implementation of the selected blocks that modify the algorithm. In particular, we focused on reducing the hardware complexity, achieving high-speed operation, while reducing energy consumption.