Modular multilevel converter (MMC) structures are composed of several hundreds to thousands of half-bridge converters. Such large numbers of power switches and electrical nodes introduce important numerical challenges for the computation of electromagnetic transients. The problem becomes particularly more complex for the real-time simulations. This paper presents a feasibility study on the real-time simulation of the MMC models. CPU-based and field-programmable gate array-based implementations are proposed and evaluated for the MMCs having up to 401 levels. The study also provides guidelines for the real-time simulation platform requirements to simulate these MMC models.

A comprehensive approach to the real-time simulation of power converters using a state-space representation is covered in this paper. Systematic formulations of state-space equations as well as a new switch model are presented. The proposed switch model exhibits a natural switching behavior, which is a valuable characteristic for the real-time simulation of power converters, thereby allowing individual treatment of switching devices irrespective of the converter topology. Successful implementations of the proposed switch model on a field programmable gate array (FPGA) device are reported, with two alternative approaches: 1) precomputing network equations for all switch state combinations and 2) solving network equations on-chip using the Gauss-Seidel iterative method. A two-level three-phase voltage source converter is implemented using the first approach, with a time step of 80 ns and a switching frequency of 200 kHz. Ideal and nonideal boost converters are also implemented on FPGA using the second approach, with a time step of 75 ns and a switching frequency of 20 kHz. Comparison with SPICE models shows that the proposed switch model offers very satisfactory accuracy and precision.

This paper evaluates the benefits of using a high-level synthesis (HLS) tool to develop field-programmable gate array (FPGA)-based real-time simulators for power electronics systems. The investigated workflow generates a synthesizable hardware description from a system level C-code along with a set of directives that specify performance criteria such as area utilization and timing closure requirements. The performance of the HLS approach is evaluated for different circuit sizes and target clock frequencies. Results show that HLS can be used for hardware-in-the-loop (HIL) applications when the circuit to be simulated is small and the target clock frequency is not too high (up to 100 MHz). For larger circuits and higher clock frequencies, HLS will either require a simulation time-step that is too large for real-time simulation purposes, or will tend to use almost all of the FPGA resources.

The realm of hardware-in-the-loop simulation resorts to field-programmable gate arrays to achieve time steps below 1 $\mu\hbox{s} $. Such low time steps are of importance for the aerospace and automotive industries, where power converters have their switching frequencies in the 10- to 200-kHz range. This paper proposes a network tearing technique that allows subsets of switches to be treated independently, alleviates embedded memory requirements, and reduces the computational burden. An iterative algorithm is used to determine the state of naturally commutated switches, thus offering a realistic model of the power converter, independently of its operation mode or topology. A Gauss-Jordan processing unit is implemented to solve interface voltages/currents from the torn circuit. Custom floating-point operators are used to ensure good accuracy, high-frequency operation, and low computational latency. A neutral-point-clamped converter case study is presented to demonstrate the effectiveness of the method. Simulation results are validated against a reference model at a 750-ns time step and a 30-kHz sine pulsewidth modulation switching frequency.

This paper presents a methodology for the central-processing unit/field-programmable gate-array (FPGA)-based real-time simulation of a two-terminal MMC-HVDC of up to 501 levels using a detailed equivalent model. The proposed modeling approach is validated using case studies of 101-level and 501-level multilevel modular converter setups. FPGA-based models are designed using low-latency custom-made floating-point operators. The FPGA model is entirely reconfigurable in terms of the number of submodules per arm, as well as circuit parameters on an individual submodule basis. Real-time simulation performance is demonstrated in single-rate and multirate simulation environments and under various operating conditions. Limitations to the detailed equivalent model are identified and discussed.

This article presents general modeling approaches to achieve an accurate real-time simulation (RTS) of high switching frequency converters.The proposed methods are based on the direct mapped method (DMM) and make use of decoupling techniques when appropriate. The DMM links state variables to diode statuses and provides an exact and noniterative solution to network equations. An electric vehicle battery charger test case comprised of a full-bridge rectifier, an interleaved boost, and a three-phase LLC is used to demonstrate the high accuracy achieved by the proposed methods compared to a conventional approach. Field-programmable gate array (FPGA) implementations are proposed and shown to achieve from 75- to 175-ns RTS time steps for this test case circuit, allowing its accurate simulation while switched at 200 kHz. To further validate the effectiveness of the FPGA-based simulator, a resonant boost converter is also implemented and simulated in real time.