Dry electrodes are a promising solution for prolonged EEG signal acquisition, whereas wet electrodes may lose their signal quality in the same situation and require skin preparation for set-up. Here, we review the impedance and noise of passive and active dry EEG electrodes. In addition, we compare noise and input impedance of the EEG amplifiers. As there are multiple definitions of impedance in each EEG system, they are all first defined. Electrodes must be compatible with amplifiers to accurately record EEG signals. This implies that their impedance plays a significant role in amplifier compatibility and affects total input-referred noise. Therefore, we review the impedance and noise of state-of-the-art amplifiers and electrodes. Furthermore, we compare the various structures and materials used and their final impedance to that of wet electrodes. Finally, we compare state-of-the-art electrodes and amplifiers to the standards of the IFCN and IEC80601-2-26. We investigate bottlenecks and propose a guideline for future work on passive and active dry electrodes, as well as EEG amplifiers.

We report on the measurements of the heterodimensional Schottky barrier height in two-dimensional metal-semiconductor field effect transistors (2D MESFETs). Our experimental data indicate approximately 0.1 eV greater barrier height compared to conventional metal-semiconductor contacts of the same materials. The enhancement is explained in terms of two effects—quantization of energy levels of the carriers in the quantum well and broadening of the corresponding wave functions. The increased barrier height leads to a substantial reduction of the gate leakage current in 2D MESFETs.

A platform for benchmarking tunnel field-effect transistors (TFETs) for analog applications is presented and used to compare selected TFETs to FinFET technology at the 14-nm node. This benchmarking is enabled by the development of a universal TFET SPICE model and a parameter extraction procedure based on data from physics-based device simulators. Analog figures of merit are computed versus current density to compare TFETs with CMOS for low-power analog applications to reveal promising directions for the system development. To illustrate the design space enabled by TFETs featuring sub-60-mV/decade subthreshold swing, two example circuits including a picopower common-source amplifier and an ultralow-voltage ring oscillator are demonstrated.

We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm × 0.35 mm, a 1.2 V supply for the core and 1.8 V for the input switches. It has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.

This article presents analytical tools for high-level design of the leapfrog (LF) control-bounded analog-to-digital converter (CBADC). We derive closed-form design equations for parameterizing the analog system for a target signal-to-noise ratio (SNR) and bandwidth. Furthermore, we show how the parameterization can be modified to compensate for finite amplifier gain-bandwidth product (GBWP) and to control the signal swing at different nodes of the system. Behavioral circuit simulations are used to compare the LF CBADC to relevant continuous-time sigma–delta modulators (CT- $\Sigma \Delta $ Ms) in terms of nominal performance and sensitivity to component variations, clock jitter, and finite GBWP. Simulations show that the nominal performance of the LF is similar to that of a CT- $\Sigma \Delta \text{M}$ of the same loop-filter order and with the same number of quantization levels. The simple, modular structure, analytical stability guarantee, and single-bit quantizers make the LF an interesting alternative to conventional CT- $\Sigma \Delta $ Ms.