This work reports a novel chaos-based affine transformation generation method, which is based on rotational matrices to design strong key-based S-boxes. Chaotic logistic map’s nonlinear trajectories are used to generate rotational matrices under given design conditions. Thus, the inherent logic is to generate key-based S-boxes, as strong as AES S-box, in terms of cryptographic properties using chaos in affine transformation. The randomness of chaotic sequences is tested using the National Institute of Standard and Technology (NIST) Statistical Test Suit (STS) 800-22 that validates the generated sequences for S-box design. The results show that methodology adapted to design proposed key-based dynamic Sboxes entails near-optimal cryptographic properties so that proposed S-boxes are as stronger as AES S-box.

Robust chaotic systems, due to their inherent properties of mixing, ergodicity, and larger chaotic parameter space, constitute a perfect candidate for cryptography. This paper reports a novel method to generate random numbers using modified robust logistic map (MRLM). The non-smooth probability distribution function of robust logistic map (RLM) trajectories gives an un-even binary distribution in randomness test. To overcome this disadvantage in RLM, control of chaos (CoC) is proposed for smooth probability distribution function of RLM. For testing the proposed design, cryptographic random numbers generated by MRLM were vetted with National Institute of Standards and Technology statistical test suite (NIST 800-22). The results showed that proposed MRLM generates cryptographically secure random numbers (CSPRNG).

The reliance on Network-on-Chip (NoC) based Multiprocessor Systems-on-Chips (MPSoCs) is proliferating in modern embedded systems to satisfy the higher performance requirement of multimedia streaming applications. Task level coarse grained software pipeling also called re-timing when combined with Dynamic Voltage and Frequency Scaling (DVFS) has shown to be an effective approach in significantly reducing energy consumption of the multiprocessor systems at the expense of additional delay. In this paper we develop a novel energy-aware scheduler considering tasks with conditional constraints on Voltage Frequency Island (VFI) based heterogeneous NoC-MPSoCs deploying re-timing integrated with DVFS for real-time streaming applications. We propose a novel task level re-timing approach called R-CTG and integrate it with non linear programming based scheduling and voltage scaling approach referred to as ALI-EBAD. The R-CTG approach aims to minimize the latency caused by re-timing without compromising on energy-efficiency. Compared to R-DAG, the state-of-the-art approach designed for traditional Directed Acyclic Graph (DAG) based task graphs, R-CTG significantly reduces the re-timing latency because it only re-times tasks that free up the wasted slack. To validate our claims we performed experiments on using 12 real benchmarks, the results demonstrate that ALI-EBAD out performs CA-TMES-Search and CA-TMES-Quick task schedulers in terms of energy-efficiency.

Multiprocessor System On Chip (MPSoC) with Networks-on-Chip (NoCs) have been proposed to address the communication challenges in modern dynamic applications. One of the key aspects of design exploration in NoC-based MPSoC is application mapping, which is critical for the parallel execution of multiple applications. However, mapping for dynamic workloads becomes challenging due to unpredictable arrival times of applications and the availability of resources. In this work, we propose a hybrid task mapping approach, HyDra, that combines design-time mapping and efficient run time remapping to reduce communication and energy costs. The proposed approach generates multiple application mappings during the design time phase by minimizing latency, energy, and communication costs. The diverse mapping possibilities produced at design time considers multiple performance metrics. However, we cannot predict the arrival time of applications and the availability of resources at design time. To further optimize the MPSoC performance, our dynamic mapping phase re configures the design time mappings based on run time availability of resources and applications. The simulation results show that HyDra reduces communication costs by 14% while using 15% less energy for small and large NoCs compared to state-of-the-art task mapping techniques. Furthermore, our approach provides an average of 19% reduction in end-to-end latency for applications. Our hybrid task allocation and scheduling approach effectively addresses communication issues in NoC-based MPSoCs for dynamic workloads. HyDra achieves improved performance by combining design-time and run time mapping, providing a promising solution for future MPSoC design.

Falls are a major public health concern among the elderly and the number of gadgets designed to detect them has increased significantly in recent years. This document provides a detailed summary of research done on fall detection systems, with comparisons across different types of studies. Its purpose is to be a resource for doctors and engineers who are planning or conducting field research. Following the examination, datasets, limitations, and future imperatives in fall detection were discussed in detail. The quantity of research using context-aware approaches continues to rise, but there is a new trend toward integrating fall detection into smartphones, as well as the use of artificial intelligence in the detection algorithm. Concerns with real-world performance, usability, and reliability are also highlighted.