Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the high-performance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results.

The fracture of the elbow is common in human beings. The complex structure of the elbow, including its irregular shape, border, etc., makes it difficult to correctly recognize elbow fractures. To address such challenges, a method is proposed in this work that consists of two phases. In Phase I, pre-processing is performed, in which images are converted into RGB. In Phase II, pre-trained convolutional models Darknet-53 and Xception are used for deep feature extraction. The handcrafted features, such as the histogram of oriented gradient (HOG) and local binary pattern (LBP), are also extracted from the input images. A principal component analysis (PCA) is used for best feature selection and is serially merged into a single-feature vector having the length of N×2125. Furthermore, informative features N×1049 are selected out of N×2125 features using the whale optimization approach (WOA) and supplied to SVM, KNN, and wide neural network (WNN) classifiers. The proposed method’s performance is evaluated on 16,984 elbow X-ray radiographs that are taken from the publicly available musculoskeletal radiology (MURA) dataset. The proposed technique provides 97.1% accuracy and a kappa score of 0.943% for the classification of elbow fractures. The obtained results are compared to the most recently published approaches on the same benchmark datasets.

Multiprocessor System On Chip (MPSoC) with Networks-on-Chip (NoCs) have been proposed to address the communication challenges in modern dynamic applications. One of the key aspects of design exploration in NoC-based MPSoC is application mapping, which is critical for the parallel execution of multiple applications. However, mapping for dynamic workloads becomes challenging due to unpredictable arrival times of applications and the availability of resources. In this work, we propose a hybrid task mapping approach, HyDra, that combines design-time mapping and efficient run time remapping to reduce communication and energy costs. The proposed approach generates multiple application mappings during the design time phase by minimizing latency, energy, and communication costs. The diverse mapping possibilities produced at design time considers multiple performance metrics. However, we cannot predict the arrival time of applications and the availability of resources at design time. To further optimize the MPSoC performance, our dynamic mapping phase re configures the design time mappings based on run time availability of resources and applications. The simulation results show that HyDra reduces communication costs by 14% while using 15% less energy for small and large NoCs compared to state-of-the-art task mapping techniques. Furthermore, our approach provides an average of 19% reduction in end-to-end latency for applications. Our hybrid task allocation and scheduling approach effectively addresses communication issues in NoC-based MPSoCs for dynamic workloads. HyDra achieves improved performance by combining design-time and run time mapping, providing a promising solution for future MPSoC design.

A Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-Pass-Mesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-Pass-Torus is an efficient candidate among its predecessor’s and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication.