This paper addresses the influences of device and circuit mismatches on paralleling the silicon carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed to reduce such a coupling effect. Finally, simulations and experimental tests are carried out to validate the analysis and effectiveness of the developed layout.

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 μF dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach.

Parallel voltage-source converters (VSCs) require an inductive filter to suppress the circulating current. The size of this filter can be minimized by reducing either the maximum value of the flux linkage or the core losses. This paper presents a modified discontinuous pulsewidth modulation (DPWM) scheme to reduce the maximum value of the flux linkage and the core losses in the circulating current filter. In the proposed PWM scheme, the dwell time of an active vector is divided within a half-carrier cycle to ensure simultaneous occurrence of the same zero vectors in both VSCs. A function to decide the ratio of the dwell time of the divided active vector is also presented. The effect of the proposed PWM scheme on the maximum value of the flux linkage and the core losses is analyzed and compared with that of the space vector modulation and 60$^\circ$ clamped DPWM schemes. The analytical expressions for the maximum value of the flux linkage are derived for each of these PWM schemes. In addition, the effect of the proposed PWM scheme on the line current ripple and the switching losses is also analyzed and compared. To verify the analysis, experimental results are presented, which prove the effectiveness of the proposed PWM scheme.

A small dc-link capacitor based drive system shows instability when it is operated with large input line inductance at operating points with high power. This paper presents a simple, new active damping technique that can stabilize effectively the drive system at unstable operating points, offering greatly reduced input line current total harmonic distortion. The proposed method requires only a first-order, high-pass filter with a gain. Active damping voltage terms, linked directly to the dc-link voltage ripple through gain units, are injected to the drive machine for stabilizing the operating points. The stabilizing effect of the active damping terms is demonstrated for an induction machine based drive system. The effects of the added damping terms on the machine current and dc-link voltage are analyzed in detail. A design recommendation for the proposed active damping terms is given. Experimental results verifying the effectiveness of the new active damping method are presented.

Squirrel cage induction motor (SQIM) fed by a pulse width modulated voltage source inverter (VSI) is subjected to voltage and current surges. It may cause additional losses in the motor, insulation failure, high bearing current, and electromagnetic interference. To mitigate these problems, sinusoidal LC filter is placed at the ac-side of the VSI. This paper proposes a new methodology to design the filter. In this method, the filter inductance is chosen based on the maximum ripple in the inverter ac-side current and the voltage drop across the filter inductor, and the filter capacitor is chosen based on the steady-state reactive power demand of the SQIM. The effects of the designed filter on the switch current, losses in the drive, temperature of the dc-link capacitor, dv/dt at the motor terminal, stator flux, and air-gap torque of the SQIM are discussed. The performance of the drive with the filters, designed by the proposed method and the standard method, are experimentally tested on a two-level Silicon carbide (SiC) VSI fed SQIM and comparative analysis is carried out. The impact of the designed filter on the drive is also shown when the neutral point of the filter capacitors is connected with the mid-point of the dc-link. The stability of the closed-loop controlled SQIM drive with the proposed filter, and simulation results are presented to verify its performance.

A novel hybrid pulse width modulation (PWM) technique is proposed in this paper for two parallel interleaved, two-level, three-phase voltage source inverters (VSIs). The two parallel interleaved VSIs are analyzed as a three-level (3L) inverter. A 3L inverter provides minimum line current ripple when nearest three voltage vectors are applied. In this paper, a novel carrier-based PWM technique is developed that ensures the application of nearest voltage vectors, keeping average circulating current to zero over a switching period. For carrier-based implementation of the proposed PWM, generalized common-mode (CM) offsets are derived in terms of maximum and minimum values of reference signals. Each 3L space-vector sector is divided into seven subsectors. For each subsector, a CM offset is calculated, addition of which to reference signals ensures the minimum line current ripple and zero average circulating current. Simulation and experimental results are provided to validate the proposed technique.