This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μV rms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology.

Wireless power and data communication systems in implantable medical devices (IMDs) are developed to control and report acquired biological data from an implanted device to an external stage in several medical applications. Ultrasonic, capacitive, optical, radio frequency (RF), and inductive links are employed as a wireless power and data transmission technique. Inductive power transfer (IPT) is one of the most commonly used techniques due to its robustness, simplicity, safety, and capability of simultaneous and bidirectional data and power transmission. This paper presents a systematic review and survey of the latest inductive power and data transmission methods for IMDs. The fundamental principles of remote powering through inductive links, the critical parameters of design, and power transfer efficiency calculations are presented. Single and multiple inductive links, the advantages and drawbacks, optimization methods, and comparison by their performances are explored. In addition, modulation schemes, along with improvement techniques reported in the literature, the strengths and limitations, and the measured or the simulated data rate of each are also reviewed. A benchmarking table with summarized design features of systems, essential parameters for wireless powering and data communication, and categorized Figure-of-Merits (FoMs) to compare performances are also provided.

This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 \mbi μm CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 \mbi μW of power within an effective area of 250 \mbi μm × 250 \mbi μm per channel.

Safety and energy efficiency are two major concerns for implantable neural stimulators. This paper presents a novel high-frequency, switched capacitor (HFSC) stimulation and active charge balancing scheme, which achieves high energy efficiency and well-controlled stimulation charge in the presence of large electrode impedance variations. Furthermore, the HFSC can be implemented in a compact size without any external component to simultaneously enable multichannel stimulation by deploying multiple stimulators. The theoretical analysis shows significant benefits over the constant-current and voltage-mode stimulation methods. The proposed solution was fabricated using a 0.18 μm high-voltage technology, and occupies only 0.035 mm ² for a single stimulator. The measurement result shows 50% peak energy efficiency and confirms the effectiveness of active charge balancing to prevent the electrode dissolution.