Waseem Abbas

Mr. Waseem Abbas

Sungkyunkwan University
orcid

Research Focus & Metrics

Academic Career Length

7Years (2020-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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16 July 2021 in IEEE Antennas and Wireless Propagation Letters
Verified
Journal Article
Closed access
Amir AltafAmir Altaf
Amir Altaf
WAWaseem Abbas
Waseem Abbas
MSMunkyo Seo
Munkyo Seo
In this letter, a wideband substrate integrated waveguide (SIW) based slot antenna is designed for D -band applications. A wideband response is attributed to the merging of closely lying six resonance frequencies. Two of them at frequencies of 114.25 GHz and 134.75 GHz signifies the excitation of TE $_{310}$ and TE $_{120}$ modes, respectively. The modes at 124 GHz and 144 GHz are identified as hybrid modes that are formed from the combination of TE $_{310}$ –TE $_{120}$ and TE $_{120}$ –TE $_{220}$ modes, respectively. The upper two resonances at the frequencies of 154 GHz and 160 GHz occur due to TE $_{220}$ –TE $_{320}$ based hybrid modes. A two-step wideband WR6-SIW transition is also designed and integrated with the antenna for measurement purpose. In the first step, the three-section Chebyshev transition is developed to match the impedance of standard WR6 with a rectangular waveguide (RWG) of the same height as that of the PCB. In the second step, the RWG is matched with SIW using a dielectric extension. The final antenna with transition is simulated and measured. A wide $-$ 10 dB impedance bandwidth for $|S_{11}| \leq -$ 10 dB of 42.86% (110–170 GHz) is obtained. The gain and radiation measurements were also performed after constructing an in-house measurement system.

13 September 2020 in Electronics
Verified
Journal Article
Open access
PDF file
WAWaseem Abbas
Waseem Abbas
ZMZubair Mehmood
Zubair Mehmood
MSMunkyo Seo
Munkyo Seo
A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.