A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm${}^2$ including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

This paper presents a high-speed V-band on-off keying (OOK) modulator in 65 nm CMOS based on distributed transmission lines architecture. The high-speed operation of the proposed OOK modulator is attained by distributing a single large switching transistor into smaller units. The effects of parasitic capacitances of each small switch are mitigated by series inductors, forming an artificial transmission line. The switch size and the number of stages are optimized for a reasonable balance between insertion loss and isolation. Small signal measurement of the OOK modulator reveals 3.8 dB insertion loss and 20.5 dB isolation at 60 GHz, with 16 dB on-off ratio from 50 GHz to 70 GHz. Testing with a modulation setup shows the modulator is fully functional up to 5 Gbps at a 60 GHz carrier. Limitations of the test setup prevent modulation testing at >5 Gbps. The fabricated modulator does not consume any DC power and has an active footprint of 0.025 mm².