An 8-bit 10-GHz 8 × time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range (SFDR) by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts.

An 8-bit 10-GHz $8\times $ time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than $2\times $ improvement from the state-of-the-art.

The Stochastic Phase-Interpolation Time-to-Digital Converter (SPI-TDC) leverages redundancy to tolerate Process-Voltage-Temperature (PVT) variations. This article presents a comprehensive analysis of the linearity of the SPI-TDC and its error mechanisms, and proposes a linearization technique to reduce the redundancy requirement. Using deterministic and stochastic models, this article analyzes the effects of the unit delay, length of the delay-line, clock frequency, jitter, and mismatch on the linearity of the SPI-TDC, and prescribes a compact set of design equations to guide the designer. Based on the results of the analysis, the article proposes a robust solution using a Delay-Locked Loop (DLL) to linearize the SPI-TDC with reduced hardware and power overhead. This article also analyzes, for the first time, the loop dynamics of a DLL accounting for the delay of the delay-line. Measurements of an 8-bit, 60-MHz SPI-TDC validate the theories and demonstrate the effectiveness of the proposed solution across supply and temperature variations while using only 4x redundancy.

A successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates “tapered bit periods" to reduce power consumption by minimizing the digital-to-analog converter (DAC) timing overhead. Utilizing a variable delay line and the standard SAR logic, the proposed technique reduces power by downsizing the DAC drivers and digital logic without decreasing the sampling rate. A detailed analysis derives, for the first time, a closed-form solution of the capacitive DAC settling time accounting for parasitics, and determines the time savings of the proposed design. In addition, this paper proposes a “partially interdigitated" DAC layout to reduce the bottom-plate parasitic capacitance to minimize the DAC power. A 9-bit prototype fabricated in 180-nm technology achieves an SNDR of 55.5 dB at a 10-MHz sampling rate while consuming 28 μW, yielding a figure-of-merit (FoM) of 5.7 fJ/conversion-step, the lowest among published ADCs at similar speeds and resolutions.

This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for low-power applications. To tolerate the severe variations in the subthreshold regime, a novel dynamic bulk biasing circuit senses the NMOS/PMOS strength ratio in the background and applies feedback to equalize the strengths to maintain the circuit functionality. A rigorous analysis examines the dynamics and convergence of the proposed biasing circuit in the time-and $z$ -domains. A new comparator relaxes the stringent speed-noise trade-off under the 0.2-V supply. Employing switched ac-coupling, stacked input pairs, and voltage-boosted load capacitors, the comparator achieves more than a threefold improvement in speed with little noise penalty. The DAC implements grouped capacitors with quantized sub-radix-2 scaling for redundancy and low power and achieves 10-bit matching. Details of the complete ADC design are described. The measured ADC consumes 22 nW and exhibits a peak DNL and INL of 0.45 LSB and 0.67 LSB, respectively. The measured SFDR and SNDR at Nyquist are 70.6 dB and 52.8 dB, respectivley, yielding an FoM of 12.3 fJ/conv.-step. Measurements show the dynamic bulk biasing compensates the N/P strength ratio variations to optimize the SNDR. We also show that the proposed dynamic bulk biasing successfully maintains the ADC performance over supply variations and improves the yield by nearly twofold over 20 chips.

A miniaturized short-wavelength infrared spectrometer for use with diffuse light was created by combining a thin form factor carbon nanotube composite collimator, a linear variable filter, and an InGaAs photodiode array. The resulting spectrometer measures 3 mm × 4 mm × 14 mm and shows a significant improvement in resolution over a spectrometer without the collimator when used with diffuse light. Its small size and high throughput make it ideal for applications such as wearable optical sensing, where light from highly scattering tissue is measured. Plethysmographic measurements on the wrist were demonstrated, showing rapid data collection with diffuse light.